參數(shù)資料
型號: μPD703003
廠商: NEC Corp.
英文描述: 16/32 Bit Single Chip Microcontrollers(16/32位單片微控制器)
中文描述: 16/32位單片機微控制器(16/32位單片微控制器)
文件頁數(shù): 72/82頁
文件大?。?/td> 592K
代理商: ΜPD703003
μ
PD703003
72
(9) CSI timing (1/2)
(a) Master mode
(i)
Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Units
MIN.
MAX.
MIN.
MAX.
SCKn cycle
<67> t
CYSK1
Output
160
120
ns
SCKn high-level width
<68> t
WSKH1
Output
0.5t
CYSK1
– 20
0.5t
CYSK1
– 20
ns
SCKn low-level width
<69> t
WSKL1
Output
0.5t
CYSK1
– 20
0.5t
CYSK1
– 20
ns
SIn setup time (to SCKn
)
<70> t
SSISK1
50
50
ns
SIn hold time (from SCKn
)
<71> t
HSKSI1
0
0
ns
SOn output delay time (to SCKn
)
<72> t
DSKSO1
18
18
ns
SOn output hold time (from SCKn
)
<73> t
HSKSO1
0.5t
CYSK1
– 5
0.5t
CYSK1
– 5
ns
Remark
n = 0 to 2
(ii) Timing of CSI3
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Units
MIN.
MAX.
MIN.
MAX.
SCK3 cycle
<67> t
CYSK3
Output
R
L
= 1.5 k
C
L
= 50 pF
500
500
ns
SCK3 high-level width
<68> t
WSKH3
Output
0.5t
CYSK3
– 150
0.5t
CYSK3
– 150
ns
SCK3 low-level width
<69> t
WSKL3
Output
0.5t
CYSK3
– 70
0.5t
CYSK3
– 70
ns
SI3 setup time (to SCK3
)
<70> t
SSISK3
100
100
ns
SI3 hold time (from SCK3
)
<71> t
HSKSI3
50
50
ns
SO3 output delay time (to SCK3
)
<72> t
DSKSO3
R
L
= 1.5 k
C
L
= 50 pF
150
150
ns
SO3 output hold time (from SCK3
)
<73> t
HSKSO3
t
WSKH3
t
WSKH3
ns
Remark
R
L
and C
L
are the load resistance and load capacitance of the output line for SCK3 and SO3.
(b) Slave mode
(i)
Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Units
MIN.
MAX.
MIN.
MAX.
SCKn cycle
<67> t
CYSK2
Input
160
120
ns
SCKn high-level width
<68> t
WSKH2
Input
50
30
ns
SCKn low-level width
<69> t
WSKL2
Input
50
30
ns
SIn setup time (to SCKn
)
<70> t
SSISK2
10
10
ns
SIn hold time (from SCKn
)
<71> t
HSKSI2
10
10
ns
SOn output delay time (to SCKn
)
<72> t
DSKSO2
45
45
ns
SOn output hold time (from SCKn
)
<73> t
HSKSO2
t
WSKH2
t
WSKH2
ns
Remark
n = 0 to 2
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