參數(shù)資料
型號： μPD4516821A
廠商： NEC Corp.
英文描述： 16M-bit Synchronous DRAM(16M 同步動態(tài)RAM)
中文描述： 1,600位同步DRAM（1,600同步動態(tài)RAM）的
文件頁數(shù)： 18/86頁
文件大?。?/td> 904K
代理商： ΜPD4516821A
μ
PD4516421A, 4516821A, 4516161A for Rev. P
18
(3/3)
Current state
CS
RAS
CAS
WE
Address
Command
Action
Notes
Write
recovering
H
×
×
×
×
DESL
Nop
→
Enter row active after t
DPL
L
H
H
H
×
NOP
Nop
→
Enter row active after t
DPL
L
H
H
L
×
BST
Nop
→
Enter row active after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
Start read, Determine AP
9
L
H
L
L
BA, CA, A10
WRIT/WRITA
New write, Determine AP
L
L
H
H
BA, RA
ACT
ILLEGAL
4
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
4
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Write
recovering with
auto precharge
H
×
×
×
×
DESL
Nop
→
Enter precharge after t
DPL
L
H
H
H
×
NOP
Nop
→
Enter precharge after t
DPL
L
H
H
L
×
BST
Nop
→
Enter precharge after t
DPL
L
H
L
H
BA, CA, A10
READ/READA
ILLEGAL
4, 9
L
H
L
L
BA, CA, A10
WRIT/WRITA
ILLEGAL
4
L
L
H
H
BA, RA
ACT
ILLEGAL
4
L
L
H
L
BA, A10
PRE/PALL
ILLEGAL
4
L
L
L
H
×
REF/SELF
ILLEGAL
L
L
L
L
Op-Code
MRS
ILLEGAL
Refreshing
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RC
L
H
H
×
×
NOP/BST
Nop
→
Enter idle after t
RC
L
H
L
×
×
READ/WRIT
ILLEGAL
L
L
H
×
×
ACT/PRE/PALL
ILLEGAL
L
L
L
×
×
REF/SELF/MRS
ILLEGAL
Mode register
accessing
H
×
×
×
×
DESL
Nop
→
Enter idle after t
RSC
L
H
H
H
×
NOP
Nop
→
Enter idle after t
RSC
L
H
H
L
×
BST
ILLEGAL
L
H
L
×
×
READ/WRITE
ILLEGAL
L
L
×
×
×
ACT/PRE/PALL/
ILLEGAL
REF/SELF/MRS
Notes 1.
H: High level, L: Low level,
×
: High or Low level (Don’t care), V: Valid data input
All entries assume that CKE was active (High level) during the preceding clock cycle.
If both banks are idle, and CKE is inactive (Low level),
μ
PD4516
×××
A will enter Power down mode. All
input buffers except CKE will be disabled.
Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
If both banks are idle, and CKE is inactive (Low level),
μ
PD4516
×××
A will enter Self refresh mode. All input
buffers except CKE will be disabled.
Illegal if t
RCD
is not satisfied.
Illegal if t
RAS
is not satisfied.
Must satisfy burst interrupt condition.
Must satisfy bus contention, bus turn around, and/or write recovery requirements.
10.
Must mask preceding data which don’t satisfy t
DPL
.
11.
Illegal if t
RRD
is not satisfied.
2.
3.
4.
5.
6.
7.
8.
9.
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