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參數(shù)資料
| 型號： | μPC8126K |
| 廠商： | NEC Corp. |
| 英文描述： | 900 MHz Band Direct Quadrature Modulator IC(900 MHz 頻帶直接積分調節(jié)器芯片) |
| 中文描述： | 900兆赫頻帶的直接正交調制器集成電路（900兆赫的頻帶直接積分調節(jié)器芯片） |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 189K |
| 代理商： | ΜPC8126K |
Preliminary Data Sheet P13488EJ1V0DS00
9
μ
PC8126K
Pin
No.
Symbol
Supply
Voltage
(V)
Pin
Voltage (V)
@3 V
Description
Equivalent Circuit
12
Qb
V
CC
/2
–
Input for Q signal.
This input impedance is 180 k
.
In case of that I/Q input signals are
single ended, V
CC
/2 biased DC
signal should be input.
In case of that I/Q input signals are
differential, amplitude of the signal is
250 mV
P-P
max.
Note
13
Q
V
CC
/2
–
Input for Q signal.
This input impedance is 180 k
.
In case of that I/Q input signals are
single ended, amplitude of the signal
is 500 mV
P-P
max.
Note
12
13
14
GND
(Modulator)
0
–
Ground pin for the modulator.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
–––––––––––––
16
V
CC
3
2.7 to 3.6
–
Supply voltage pin for the output
buffer amplifier of modulator.
An internal regulator helps keep the
device stable against temperature or
V
CC
variation.
–––––––––––––
17
MODout
–
1.6
Output pin from the modulator.
This is emitter follower output.
So this output impedance is low.
17
19
GND
(Modulator)
0
–
Ground pin for the modulator.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
–––––––––––––
Power save control pin can control
the On/Sleep state with bias as
follows.
V
PS
(V)
State
2.2 to 3.6
ON (Active Mode)
0 to 0.5
OFF (Sleep Mode)
20
V
PS
2
(Pre-Mix)
V
PS
–
20
Note
Relations between amplitude and V
CC
/2 bias of input signal are following.
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