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參數(shù)資料
| 型號(hào)： | μPC8126K |
| 廠商： | NEC Corp. |
| 英文描述： | 900 MHz Band Direct Quadrature Modulator IC(900 MHz 頻帶直接積分調(diào)節(jié)器芯片) |
| 中文描述： | 900兆赫頻帶的直接正交調(diào)制器集成電路（900兆赫的頻帶直接積分調(diào)節(jié)器芯片） |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 189K |
| 代理商： | ΜPC8126K |
Preliminary Data Sheet P13488EJ1V0DS00
8
μ
PC8126K
PIN EXPLANATIONS
Pin
No.
Symbol
Supply
Voltage
(V)
Pin
Voltage (V)
@3 V
Description
Equivalent Circuit
2
LOinb
–
2.6
Bypass of LO input for modulator.
This pin should be externally
grounded through around 33 pF
capacitor.
4
LOin
–
2.6
LO input for the phase shifter.
Connect around 300
between pin
4 and 5 to match to 50
by LC.
2
4
6
V
CC
2
2.7 to 3.6
–
Supply voltage pin for the phase
shifter and IQ Mixer. An internal
regulator helps keep the device
stable against temperature or V
CC
variation.
–––––––––––––
7
V
PS
1
(Modulator)
V
PS
–
Power save control pin for the
modulator can control On/Sleep
state with bias as follows.
V
PS
(V)
State
2.2 to 3.6
ON (Active Mode)
0 to 0.5
OFF (Sleep Mode)
7
9
GND
(Modulator)
0
–
Ground pin for the modulator.
Connect to the ground with minimum
inductance.
Track length should be kept as short
as possible.
–––––––––––––
10
I
V
CC
/2
–
Input for I signal.
This input impedance is 180 k
.
In case of that I/Q input signals are
single ended, amplitude of the signal
is 500 mV
P-P
max.
Note
11
Ib
V
CC
/2
–
Input for I signal.
This input impedance is 180 k
.
In case of that I/Q input signals are
single ended, V
CC
/2 biased DC
signal should be input.
In case of that I/Q input signals are
differential, amplitude of the signal is
250 m V
P-P
max.
Note
10
11
Note
Relations between amplitude and V
CC
/2 bias of input signal are following.
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