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參數(shù)資料
| 型號： | ZR36053TQC30 |
| 英文描述： | Fast Recovery Rectifier Diodes |
| 文件頁數(shù)： | 3/16頁 |
| 文件大小： | 228K |
| 代理商： | ZR36053TQC30 |
ZR36011
3
PRELIMINARY
MODE(2-0)
Input
Component decimation mode control. The decimation and interpolation modes are selected using MODE as
shown follows:
BYPASS
Input
Conversion bypass control. If BYPASS is high, the color space conversion computation is bypassed, but all deci-
mation mode selections and control inputs are still operational. The data pipeline delay of 8 clock cycles is not
affected by the activation of BYPASS.
Table 1. Signal Description (Continued)
Name
Type
Description
Decimation Mode Selection (0=low, 1=high)
MODE2
MODE1
MODE0
Description
0
0
0
4:4:4, no decimation or interpolation
0
0
1
4:2:2 chrominance decimation or interpolation without filtering
0
1
0
4:2:2 chrominance decimation or interpolation with filtering
0
1
1
4:1:1 chrominance decimation or interpolation
1
0
0
Not used
1
0
1
Not used
1
1
0
4:4:4, with 2 to 1 decimation or interpolation of all three YCbCr
components
1
1
1
4:2:2, with 2 to 1 additional decimation or interpolation of all
three YCbCr components
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