
Z8 Microcontrollers
Instruction Descriptions and Formats
ZiLOG
12-78
UM001600-Z8X0599
TM
TEST UNDER MASK
Example
Working Register R14 contains the value F3H (11110011B), Working Register R5 contains CBH, and
Register CBH contains 88H (10001000B) (bit 7 a bit 3 are being tested if they are 0), the statement:
TM R14, @R5
Op Code: 73 E5
will reset the Z Flag, because bit 7 iin the destination operand is not a 0. The S Flag will be set, and the
V Flag is cleared.
Example:
If Register D4H contains the value 08H (00001000B), and Working Register R0 contains the value 04H
(00000100B) (bit 2 is being tested if it is 0), the statement:
TM D4H, R0
Op Code: 74 E0 D4
will set the Z Flag, because bit 2 in the destination operand is a 0. The S and V Flags will be cleared.
Example:
If Register DFH contains the value 00H (00000000B), Register 07H contains the value 1FH, and Register
1FH contains the value BDH (10111101B) (bit 7, bit 5, bit 4, bit 3, bit 2, and bit 0 are being tested if they
are 0), the statement:
TM DFH, @07H
Op Code: 75 07 DF
will set the Z Flag indicating the tested bits in the destination operand are 0. The S is set, and the V Flag
is cleared.
Example:
If Working Register R13 contains the value F1H (11110001B), the statement:
TM R13, #02H
Op Code: 76 ED, 02
tests bit 1 of the destination operand for 0. The Z Flag will be set indicating bit 1 in the destination operand
was 0. The S and V Flags are cleared.
Example:
If Register 5DH contains A0H, and Register A0H contains 0FH (00001111B), the statement:
TM @5D, #10H
Op Code: 77 5D 10
tests bit 4 of the Register A0H for 0. The Z Flag will be set indicating bit 4 in the destination operand was
0. The S and V Flags are cleared.