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參數(shù)資料
| 型號： | Z0220122VSCR3470 |
| 英文描述： | 64Mb Q-Flash - OBSOLETE |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 41/48頁 |
| 文件大?。?/td> | 1331K |
| 代理商： | Z0220122VSCR3470 |
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Z02202
ZiLOG
V.22bis Data Pump with Integrated AFE
PS000902-0501
Z02201
41
4.
If
RXERROR
is
0
and
EOF
is
1
, then an HDLC frame
with a correct checksum has been received.
5.
If Byte1–ByteN+3 have been read, with ByteN+3 being
the
DATAP
value just read, then the two previous bytes
(ByteN+1 and ByteN+2), are the frame checksum bytes;
the remaining bytes (Byte1–ByteN) are the frame data
bytes.
6.
Continue from step 1 to receive the next frame. If
RXERROR is 1, discard any received frame bytes and
continue from step 1 to receive the next frame.
7.
If
DATAP
was
0FF
, an HDLC abort sequence was
received. If
DATAP
was
07EH
, an HDLC frame with an
incorrect checksum was received.
GETTING THE DATA PUMP FIRMWARE VERSION NUMBER AND PART NUMBER
The data pump code version can be obtained any time the
RAM location
CONFIG
register, bits 0–6 (
MODE
) is set to
0
. The data pump writes the part number to data pump RAM
location 0 and the code version number to the DATAP
register. To obtain the version and part number from the
data pump, the following steps must be performed:
1. Set
CONFIG
register, bits 0–6 (
MODE
) to
0
(
STANDBY
), then read location Config to provide the
data pump enough time to begin standby operation.
2. Read the
DATAP
register. This register returns the
code release version number (an 8 bit value, for
example,
030H
indicates version 30).
3. Read RAM location 0. This location returns the part
number (for example,
02201H
for a Z02201 part).
SLEEP MODE
The data pump incorporates a low-power sleep mode. In this
mode, the data pump clock is shut down, effectively
stopping the part. To enter
SLEEP
mode, the controller can
set Config to mode 7. To exit
SLEEP
mode, the controller
can either reset the data pump (asserting the
RESET
signal)
or write any value to the
DATAP
register. The host must
then wait at least 2 msec before accessing the data pump
registers.
TYPICAL PERFORMANCE DATA
The Bit Error Rate (
BER
) and Block Error Rate (
BLER
)
curves in Figure 11 and Figure 12 represent typical
performance over a variety of signal to noise conditions
(SNR).
Note:
Modems usually exhibit lower bit error rates receiving
in the low band as opposed to the high band.
When an analog link is completed, the Adaptive Equalizer
(
AEQ
) is frozen. The noise level is then increased without
making new links. These tests were conducted using a
Consultronics TCS500 Telephone Line Simulator, and a
Hewlett Packard 4951B protocol analyzer/BERT tester
under the following conditions:
Table 23. Performance Testing Conditions
Line Simulation
Transmit Level
Receive Level
Data Transmitted
Number of Bits Sent
Number of Blocks Sent
Bits per Block
AEQ
Flat
–
10 dBm
–
16.0 dBm
511 pseudo-random pattern
1,000,000
1,000
1,000
Frozen after link
establishment
C-message
Noise Calibration
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