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| 型號： | Z0220122VSCR3470 |
| 英文描述： | 64Mb Q-Flash - OBSOLETE |
| 中文描述： | 通信集成電路 |
| 文件頁數(shù)： | 20/48頁 |
| 文件大?。?/td> | 1331K |
| 代理商： | Z0220122VSCR3470 |
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Z02201
V.22bis Data Pump with Integrated AFE
ZiLOG
20
Z02201
PS000902-0501
RAMI, RXI, AND TXI INTERRUPTS
The three most significant bits in the RAM Control and data
pump status registers define the interrupt masks for
RAMI
,
RXI
, and
TXI
. A logical AND operation is performed with
the
RAMIE
,
RXIE
, and
TXIE
enable bits of the RAM Control
register and the corresponding interrupt bits in the
DATA
PUMP STATUS
register. Then, a logical OR operation is
performed on the outputs driving the
HIRQ
pin, providing
an interrupt to the host interrupt (See Figure 8).
INTERFACE RAM
The interface RAM is used by the data pump for normal
operations. All writes to the interface RAM should be Read-
Modify-Write, where only the bits that must be changed are
affected. All undocumented bits are reserved and must be
left intact.
Notes:
1. Data pump RAM reads or writes requires ap-
proximately 0.1 msec to complete.
2. Data pump RAM writes take effect at different
times, depending upon the location being written
to. During data modes, writes typically take ef-
fect at the end of the next baud period. During
other modes of operation, writes take effect in
0.1 msec.
3. Writing Reg4, for example, to set Reg4, bit 7
(TXIE) to 0 in an interrupt handler while waiting
for the data pump to set Reg4, bit 1 (RAMRQ) to
0 in the background, may cause unwanted side ef-
fects. Setting Reg4, bit 1 (RAMRQ) to 1 may
cause the data pump to repeat the read/write re-
quest if the data pump had just set Reg4, bit 1
(RAMRQ) to 0; however, setting Reg4, bit 1
(RAMRQ) to 0 may abort the RAM read/write re-
quest.
DATA PUMP INTERFACE RAM ACCESS METHOD
To write to the data pump RAM:
1. Write data to
RAMDL
&
RAMDH
.
2. Write the lower 8 bits of the address of the data pump
RAM location to register
RAMAL
.
3.
With one write operation to register R4, set the high bit
of the data pump RAM address in R4,
RAMAH
, set R4,
bit
2
(
RAMRW
) to
1
, and set R4, bit
1
(
RAMRQ
) to
1
.
4. Wait until the data pump sets R4, bit
1
(
RAMRQ
) to
0
.
To read from data pump RAM:
1. Write the lower 8 bits of the address of the data pump
RAM location to register
RAMAL
.
2.
With one write operation to register R4, set the high bit
of the data pump RAM address in R4,
RAMAH
, set R4,
bit
2
(
RAMRW
) to
0
, and set R4, bit
1
(
RAMRQ
) to
1
.
3. Wait until
RAMRQ
is reset to
0
by the data pump or
until
RAMIE
is set to
1
.
4. Read data from
RAMDL
and
RAMDH
.
Reads and writes to the data pump RAM may require 105
μ
s
to complete.
Figure 8. Host Interrupt Circuit Diagram
RAMIE
RAMI
RXIE
RXI
TXIE
TXI
HIRQ
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