參數(shù)資料
型號(hào): Z0220112VSCR4078
英文描述: MODEM
中文描述: 調(diào)制解調(diào)器
文件頁(yè)數(shù): 7/48頁(yè)
文件大?。?/td> 1331K
代理商: Z0220112VSCR4078
Z02202
ZiLOG
V.22bis Data Pump with Integrated AFE
PS000902-0501
Z02201
7
RXI
Receive Differential Analog Input Negative
(Analog Input).
RXI+
Receive Differential Analog Input Positive
(Analog Input).
TEST1
Test Pin 1
(Input, Active High).
This pin is a test
pin and must be tied to digital ground.
TEST2/RCLK
Test Pin 2, Receive Data Clock
(Output,
Active High).
This pin is a test pin and must be tied to digital
ground through a pull-down resistor. The resistor should be
Low enough to ensure this pin floats below 0.8V when the
part is in the
RESET
state. After
RESET
, this pin becomes
the Receive Data Clock Output. The resistor should be high
enough such that the output can be driven to logic
1
. This
pin is a synchronous data clock used to transfer serial data
between the data pump and the host. The clock frequencies
are 2400, 1200, and 300 Hz corresponding to the supported
data bit rates.
Vref
Reference Voltage
(Output, Active High.
An
internally generated reference voltage.
XTAL
Crystal
(Output, Active High).
Crystal oscillator
connection. This pin must be left open if an external clock
is used instead of a crystal. The data pump chip can be
connected to an external crystal circuit consisting of
24.576-MHz (parallel resonant) crystal, a resistor, and two
capacitors.
EXTAL External Clock/
Crystal
(Input, Active High).
Crystal oscillator connection. An external clock can be
input to the Z02280 on this pin when a crystal is not used.
The oscillator input is not a TTL level (see DC
characteristics in Table 4).
CF1 and CF2
Integration Capacitor Pins 1 and 2
(Analog Input).
Connect an 82pF capacitor between CF2
and CF1 to complete the internal feedback integration filter
for improved Analog-to-Digital (A/D) conversion
performance.
GND
Digital ground–
0 Volts
.
V
DD
Digital Power
5 Volts
.
AV
DD
Analog Power
5 Volts
.
AGND
Analog Ground
0 Volts
.
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相關(guān)代理商/技術(shù)參數(shù)
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