參數(shù)資料
型號(hào)： Z0220112VSCR4078
英文描述： MODEM
中文描述： 調(diào)制解調(diào)器
文件頁數(shù)： 18/48頁
文件大?。?/td> 1331K
代理商： Z0220112VSCR4078
Z02201
V.22bis Data Pump with Integrated AFE
ZiLOG
18
Z02201
PS000902-0501
Table 12. REG5: Data Pump Status Register
SYMBOL
RES
POSITION
REG 5, bit 0
NAME AND DESCRIPTION
Data Pump in RESET Mode. This bit is set whenever the data pump is in
RESET mode because of a hardware reset or power-on. The data pump sets
RES to 0 when it completes the reset cycle.
Carrier Detect. The data pump sets CDET to 1 when it enters any data mode
and is ready to transmit data. The data pump sets CDET to 0 during retrains
(see Reg5, bit 2, RTRND), and when no signal is detected from the remote
modem. See locations RLSDOnThresh and RLSDOffThresh for more
information. CDET is inverted and re
fl
ected on the data pump
’
s RLSD pin. If
CDET is 1, RLSD is Low (asserted). At any reset, or when the host sets
Config
register, bits 0–6 (
MODE
)
to 0 (STANDBY), the data pump sets CDET to 0.
Retrain Detect, 2400 bps (V.22bis data mode only).
The
Retrain sequence is
detected when this bit is set. The data pump has detected a retrain request
sequence from the remote modem.
Reserved bit location.
Data Pump Busy. This bit is set whenever the data pump starts transmitting
data and RTSP is 1. When the link is to be terminated, setting RTSP to 0
causes this bit to be reset after the data pump has
fi
nished transmitting the
most recent data in its internal buffers. When this bit has been reset, it is safe
to set Con
fi
g. register, bits 0
–
6 (MODE) to standby mode (0) and hang up the
telephone, terminating the connection. This bit also indicates when digits are
being dialed during timed dialing operation. At any reset, or when the host
sets Con
fi
g register, bits 0
–
6
(
MODE
)
to 0 (STANDBY) the data pump sets
DPBUSY to 0. This bit is not valid during HDLC operation.
Data Pump RAM Interrupt Status. This bit is set when the data pump has
processed a RAM read/write request.
Receive Interrupt Status. This bit is set when the data pump is in parallel
data transfer mode (TPDM is 1) and the data pump has written a new octet to
the DATAP register. A read from the DATAP register clears this bit.
Transmit Interrupt Status. This bit is set when the data pump is in parallel
data transfer mode (TPDM is 1) and the data pump has read the DATAP
register. A write to the DATAP register clears this bit.
Note:
The RXI bit is set to 1 after the reset sequences. All other bits in this register (Reg. 5) default to 0 at power up or after
reset sequences are completed.
CDET
REG 5, bit 1
RTRND
REG 5, bit 2
Reserved
DPBUSY
REG 5, bit 3
REG 5, bit 4
RAMl
REG 5, bit 5
RXl
REG 5, bit 6
TXl
REG 5, bit 7
Bit
7
6
5
4
3
2
1
0
TXI
RXI
RAMI
DPBUSY
RTRND
CDET
RES
Reserved
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Z0220112VSGR4078TR 制造商:Zilog Inc 功能描述:
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