REV. 1.0.1 3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC AD6 RxSDCCVAL O CMOS Receive - Section DCC Output Port - DCC Value Indic" />
參數(shù)資料
型號： XRT94L31IB
廠商： Exar Corporation
文件頁數(shù)： 118/133頁
文件大?。?/td> 0K
描述： IC MAPPER DS3/E3/STS-1 504TBGA
標(biāo)準(zhǔn)包裝： 24
應(yīng)用： 網(wǎng)絡(luò)切換
接口： 總線
電源電壓： 3.14 V ~ 3.47 V
封裝/外殼： 504-LBGA
供應(yīng)商設(shè)備封裝： 504-TBGA（35x35）
包裝： 托盤
安裝類型： 表面貼裝
XRT94L31
85
REV. 1.0.1
3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
AD6
RxSDCCVAL
O
CMOS
Receive - Section DCC Output Port - DCC Value Indicator Output
pin:
This output pin, along with the RxTOHClk and the RxSDCC output pins
function as the Receive Section DCC output port of the XRT94L31.
This output pin pulses "High" coincident to when the Receive Section
DCC output port outputs a DCC bit via the RxSDCC output pin.
This output pin is updated upon the falling edge of RxTOHClk.
The Section DCC HDLC Controller circuitry that is interfaced to this out-
put pin, the RxSDCC and the RxTOHClk pins is suppose to do the fol-
lowing.
It should continuously sample and monitor the state of this output pin
upon the rising edge of RxTOHClk.
Anytime the Section DCC HDLC circuitry samples this output pin being
"High", it should sample and latch the data on the RxSDCC output pin
(as a valid Section DCC bit) into the Section DCC HDLC circuitry.
AF4
RxE1F1E2VAL
O
CMOS
Receive - Order Wire Output Port - E1F1E2 Value Indicator Output
Pin:
This output pin, along with the RxTOHClk, RxE1F1E2FP, RxE1F1E2
and RxTOHClk output pins function as the Receive - Order Wire Output
Port of the XRT94L31.
This output pin pulses "High" coincident to when the Receive - Order
Wire output port outputs the contents of an E1, F1 or E2 byte, via the
RxE1F1E2 output pin.
This output pin is updated upon the falling edge of RxTOHClk.The
Receive Order-Wire circuitry, that is interfaced to this output pin, the
RxE1F1E2 and the RxTOHClk pins is suppose to do the following.
It should continuously sample and monitor the state of this output pin
upon the rising edge of RxTOHClk.
Anytime the Receive Order-Wire circuitry samples this output pin being
"High", it should sample and latch the data on the RxE1F1E2 output pin
(as a valid Order-wire bit) into the Receive Order-Wire circuitry.
AE6
RXPOH
O
CMOS
Receive AU-4/VC-4/STS-3c Mapper POH Processor Block - Path
Overhead Output Port - Output Pin:
This output pin, along with the RxPOHClk, RxPOHFrame and RxPOH-
Valid function as the AU-4/VC-4 Mapper POH Processor block - POH
Output port.
These pins serially output the POH data that have been received by the
Receive AU-4/VC-4 Mapper POH Processor block (via the incoming
STS-3 data-stream). Each bit, within the POH bytes is updated (via
these output pins) upon the falling edge of RxPOHClk. As a conse-
quence, external circuitry receiving this data, should sample this data
upon the rising edge of RxPOHClk.
PIN DESCRIPTION OF THE XRT94L31 (REV. B)
PIN #
SIGNAL NAME
I/O
TYPE
DESCRIPTION
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