參數(shù)資料
型號: XRT91L82IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁數(shù): 51/59頁
文件大?。?/td> 414K
代理商: XRT91L82IB
xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
48
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
0
X
3C
H
B
IT
D
ESCRIPTION
D3
INTERM
Transmit Parallel Bus Input Internal Termination
Provides 100
line-to-line internal termination to TXDI[15:0]P/N
and TXPCLKIP/N.
"Low" = Disabled
"High" = TXDI[15:0]P/N and TXPCLKIP/N internally terminated.
R/W
0
D2
SEREFDIS
SE_REF Power down Control
Powers down SE_REF and reduces power consumption.
"0" = SE_REF Enabled
"1" = SE_REF Disabled
R/W
1
D1
TXSWING
Serial CML Optical Transceiver Swing Select
This bit is used to select the output swing of the high-speed CML
interface to the optical transceiver.
"0" = Low Swing Mode CML Output Selected
"1" = High Swing Mode CML Output Selected
See Table 12 in “Section 3.9, Transmit Serial Output Control” on
page 28.
R/W
1
D0
POLARITY
Polarity for SDEXT Input
Controls the Signal Detect polarity convention of SDEXT.
"0" = SDEXT is active "Low"
"1" = SDEXT is active "High"
R/W
1
D
EVICE
"ID" R
EGISTER
(0
X
3C
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
D7
D6
D5
D4
D3
D2
D1
D0
Device "ID"
MSB
The device "ID" of the XRT91L82 LIU is 0x8003h. Along with the
revision "ID", the device "ID" is used to enable software to identify
the silicon adding flexibility for system control and debug.
RO
1
0
0
0
0
0
0
0
C
ONFIGURATION
C
ONTROL
R
EGISTER
(0
X
07
H
)
B
IT
N
AME
F
UNCTION
Register
Type
Default
Value
(HW reset)
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