參數(shù)資料
型號: XRT91L82IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁數(shù): 26/59頁
文件大?。?/td> 414K
代理商: XRT91L82IB
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.0.5
23
3.0
TRANSMIT SECTION
The transmit section of the XRT91L82 accepts 16-bit parallel data and converts it to serial CML data output
intented to interface to an optical module. It consists of a 16-bit parallel Differential LVPECL/LVDS, or Single-
Ended LVPECL interface, a 16x9 FIFO, Parallel-to-Serial Converter, a clock multiplier unit (CMU), a Current
Mode Logic (CML) differential line driver, and Loop Timing modes. The CML serial data output rate is 2.488/
2.666 Gbps for STS-48 applications. The high frequency serial clock is synthesized by a PLL, which uses a low
frequency clock as its input reference. In order to synchronize the data transfer process, the synthesized
2.488/2.666 GHz serial clock output is divided by sixteen and the 155.52/166.63 MHz clock is presented to the
upstream device to be used as its timing source.
3.1
Transmit Parallel Interface
The parallel data from an upstream device is presented to the XRT91L82 through a 16-bit Differential LVPECL/
LVDS/Single-Ended LVPECL parallel bus interface TXDI[15:0]P/N. The data is latched into a parallel input
register on the rising edge of TXPCLKIP/N. If the SONET Framer/ASIC is synchronized to the same timing
source as the XRT91L82, the transmit data and clock input can directly interface to the STS-48/STM-16
transceiver. However, if the SONET Framer/ASIC is synchronized to a separate crystal, the XRT91L82 has
two clock output references that can be used to synchronize the SONET Framer/ASIC. TXPCLKOP/N is a
155.52/166.63 MHz Differential LVPECL/LVDS or Single-Ended LVPECL clock output source that is derived
from the CMU synthesized clock. TXCLKO16P/N is a 155.52/166.63 MHz or 19.44/20.83 MHz Differential
LVPECL/LVDS or Single-Ended LVPECL auxiliary clock output source that is also derived from the CMU
sythensized clock. Either of these two clock output sources can be used to synchronize the SONET Framer/
ASIC to the XRT91L82. A simplified block diagram of the parallel interface is shown in Figure 10.
F
IGURE
10. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
SONET Framer/ASIC
TXPCLKIP/N
TXPCLKOP/N
TXCLKO16P/N
TXCLKO16SEL
XRT91L82
STS-48/STM-16
Transceiver
TXDI[15:0]P/N
16
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