
XRT86VL38
104
REV. V1.2.1
OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
T
ABLE
95: B
LOCK
I
NTERRUPT
S
TATUS
R
EGISTER
(BISR) H
EX
A
DDRESS
: 0
X
nB00
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Sa6
RO
0
Sa6 Block Interrupt Status
This bit Indicates whether or not the SA 6 block has an interrupt
request awaiting service.
0 - Indicates no outstanding SA 6 block interrupt request is awaiting
service
1 - Indicates the SA 6 block has an interrupt request awaiting ser-
vice. Interrupt Service routine should branch to the interrupt source
and read the SA6 block Interrupt Status register (address 0xnB0C)
to clear the interrupt
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the SA6 Interrupt Status Register
6
Reserved
For T1 mode only
5
RxClkLOS
RO
0
Loss of Recovered Clock Interrupt Status
This bit Indicates whether or not the Recovered Clock has an inter-
rupt request awaiting service.
0 - Indicates no outstanding SA 6 block interrupt request is awaiting
service
1 - Indicates the SA 6 block has an interrupt request awaiting ser-
vice.
This bit indicates whether or not the framer has experienced a Loss
of Recovered Clock interrupt since last read of this register.
0 = Indicates Loss of Recovered Clock interrupt has not occurred
since last read of this register
1 = Indicates Loss of Recovered Clock interrupt has occurred since
last read of this register.
N
OTE
:
This bit is only active if the clock loss detection feature is
enabled (Register - 0xn100)
4
ONESEC
RO
0
One Second Interrupt Status
This bit indicates whether or not the framer has experienced a One
Second interrupt since the last read of this register.
0 = Indicates One Second interrupt has not occurred since the last
read of this register
1 = Indicates One Second interrupt has occurred since the last read
of this register
3
HDLC
RO
0
HDLC Block Interrupt Status
This bit indicates whether or not the HDLC block has any interrupt
request awaiting service.
0 = Indicates no outstanding HDLC block interrupt request is await-
ing service
1 = Indicates HDLC Block has an interrupt request awaiting service.
Interrupt Service routine should branch to the interrupt source and
read the corresponding Data Link Status Registers (address
0xnB06, 0xnB16, 0xnB26, 0xnB10, 0xnB18, 0xnB28) to clear the
interrupt.
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Data Link Status
Registers that generated the interrupt.