參數(shù)資料
型號： XRT86VL38_2
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 67/160頁
文件大小： 860K
代理商： XRT86VL38_2
XRT86VL38
62
REV. V1.2.0
OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
2
Tx_IDLE
R/W
0
Transmit Idle (Flag Sequence Byte)
This bit configures the Transmit HDLC Controller Block #2 to uncon-
ditionally transmit a repeating string of Flag Sequence octets (0X7E)
in the data link channel to the Remote terminal. In normal condi-
tions, the Transmit HDLC Controller block will repeatedly transmit
the Flag Sequence octet whenever there is no MOS message to
transmit to the remote terminal equipment. However, if the user
invokes this “Transmit Idle Sequence” feature, then the Transmit
HDLC Controller block will UNCONDITIONALLY transmit a repeat-
ing stream of the Flag Sequence octet (thereby overwriting all out-
bound MOS data-link messages).
0 - Configures the Transmit HDLC Controller Block # 2 to transmit
data-link information in a “normal” manner.
1 - Configures the Transmit HDLC Controller block # 2 to transmit a
repeating string of Flag Sequence Octets (0x7E).
N
OTE
:
This bit is ignored if the
Transmit
HDLC2 controller is
operating in the BOS Mode - bit 0 (MOS/BOS) within this
register is set to 0.
1
Tx_FCS_EN
R/W
0
Transmit LAPD Message with Frame Check Sequence (FCS)
This bit permits the user to configure the Transmit HDLC Controller
block # 2 to compute and append FCS octets to the “back-end” of
each outbound MOS data-link message.
0 - Configures the Transmit HDLC Controller block # 2 to NOT com-
pute and append the FCS octets to the back-end of each outbound
MOS data-link message.
1 - Configures the Transmit HDLC Controller block # 2 TO COM-
PUTE and append the FCS octets to the back-end of each outbound
MOS data-link message.
N
OTE
:
This bit is ignored if the transmit HDLC2 controller has been
configured to operate in the BOS mode - bit 0 (MOS/BOS)
within this register is set to 0.
0
MOS/BOS
R/W
0
Message Oriented Signaling/Bit Oriented Signaling Send
This bit permits the user to enable LAPD transmission through
HDLC Controller Block # 2 using either BOS (Bit-Oriented Signaling)
or MOS (Message-Oriented Signaling) frames.
0 - Transmit HDLC Controller block # 2 BOS message Send.
1 - Transmit HDLC Controller block # 2 MOS message Send.
N
OTE
:
This is not an Enable bit. This bit must be set to "0" each time
a BOS is to be sent.
T
ABLE
44: D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR2) H
EX
A
DDRESS
: 0
X
n143
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
相關(guān)PDF資料
PDF描述
XRT86VL38IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38IB484 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VL38ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38ES484 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8 IND FULL DPLX FIFO TWO-FRAME CAS CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38IB484 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 8 IND FULL DPLX FIFO TWO-FRAME CAS CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38IB484-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
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