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參數(shù)資料
型號： XRT86VL34IB-F
廠商： Exar Corporation
文件頁數(shù)： 51/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 4CH 225BG
標準包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應商設備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL34
139
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.1
NOTE: Register 0x0FN4, 0x0FN5 and 0x0FN6 only work if the LIU is placed in Single Rail mode. If done so, the Framer
block must also be placed in Single Rail mode in Register 0xn101.
3
NLCDIS_n
RUR/
WC
0
Change in Network Loop-Code Detection Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change in
Network Loop-Code Detection” Interrupt has occurred since the last
read of this register.
0 = Indicates that the “Change in Network Loop-Code Detection”
Interrupt has NOT occurred since the last read of this register.
1 = Indicates that the “Change in Network Loop-Code Detection”
Interrupt has occurred since the last read of this register.
This bit is set to a “1” every time when NLCD status bit (bit 3 of Reg-
ister 0x0Fn5) has changed since the last read of this register.
NOTE: Users can determine the current state of the “Network Loop-
Code Detection” by reading out the content of bit 3 within
Register 0x0Fn5
2
Reserved
-
This bit is not used
1
RLOSIS_n
RUR/
WC
0
Change of Receive LOS (Loss of Signal) Defect Condition Inter-
rupt Status:
This RESET-upon-READ bit indicates whether or not the “Change of
the Receive LOS Defect Condition” Interrupt has occurred since the
last read of this register.
0 = Indicates that the “Change of the Receive LOS Defect Condi-
tion” Interrupt has NOT occurred since the last read of this register.
1 - Indicates that the “Change of the Receive LOS Defect Condition”
Interrupt has occurred since the last read of this register.
NOTE: The user can determine the current state of the “Receive
LOS Defect condition” by reading out the contents of Bit 1
(Receive LOS Defect Condition Status) within Register
0xnFn5.
0
QRPDIS_n
RUR/
WC
0
Change in Quasi-Random Pattern Detection Interrupt Status:
This RESET-upon-READ bit indicates whether or not the “Change in
QRSS Pattern Detection” Interrupt has occurred since the last read
of this register.
0 = Indicates that the “Change in QRSS Pattern Detection” Interrupt
has NOT occurred since the last read of this register.
1 = Indicates that the “Change in QRSS Pattern Detection” Interrupt
has occurred since the last read of this register.
This bit is set to a “1” every time when QRPD status bit (bit 0 of Reg-
ister 0x0Fn5) has changed since the last read of this register.
NOTE: Users can determine the current state of the “QRSS Pattern
Detection” by reading out the content of bit 0 within Register
0x0Fn5
TABLE 113: LIU CHANNEL CONTROL INTERRUPT STATUS REGISTER (LIUCCISR)
HEX ADDRESS: 0X0FN6
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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