TABLE
參數(shù)資料
型號(hào)： XRT86VL34IB-F
廠商： Exar Corporation
文件頁數(shù)： 21/155頁
文件大?。?/td> 0K
描述： IC LIU/FRAMER T1/E1/J1 4CH 225BG
標(biāo)準(zhǔn)包裝： 84
控制器類型： T1/E1/J1 調(diào)幀器，LIU
電源電壓： 3.3V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 225-BGA
供應(yīng)商設(shè)備封裝： 225-BGA（19x19）
包裝： 托盤
XRT86VL34
112
REV. V1.2.1
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
TABLE 96: DATA LINK STATUS REGISTER 2 (DLSR2)
HEX ADDRESS: 0XnB16
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
7
MSG TYPE
RO
0
HDLC2 Message Type Identifier
This READ ONLY bit indicates the type of data link message
received by Receive HDLC 2 Controller. Two types of data link mes-
sages are supported within the XRT86VL34 device: Message Ori-
ented Signaling (MOS) or Bit-Oriented Signalling (BOS).
0 = Indicates Bit-Oriented Signaling (BOS) type data link message is
received
1 = Indicates Message Oriented Signaling (MOS) type data link
message is received
6
TxSOT
RUR/
WC
0
Transmit HDLC2 Controller Start of Transmission (TxSOT)
Interrupt Status
This Reset-Upon-Read bit indicates whether or not the “Transmit
HDLC2 Controller Start of Transmission (TxSOT) “Interrupt has
occurred since the last read of this register. Transmit HDLC2 Con-
troller will declare this interrupt when it has started to transmit a data
link message. For sending large HDLC messages, start loading the
next available buffer once this interrupt is detected.
0 = Transmit HDLC2 Controller Start of Transmission (TxSOT) inter-
rupt has not occurred since the last read of this register
1 = Transmit HDLC2 Controller Start of Transmission interrupt
(TxSOT) has occurred since the last read of this register.
5
RxSOT
RUR/
WC
0
Receive HDLC2 Controller Start of Reception (RxSOT) Interrupt
Status
This Reset-Upon-Read bit indicates whether or not the Receive
HDLC2 Controller Start of Reception (RxSOT) interrupt has
occurred since the last read of this register. Receive HDLC2 Con-
troller will declare this interrupt when it has started to receive a data
link message.
0 = Receive HDLC2 Controller Start of Reception (RxSOT) interrupt
has not occurred since the last read of this register
1 = Receive HDLC2 Controller Start of Reception (RxSOT) interrupt
has occurred since the last read of this register
4
TxEOT
RUR/
WC
0
Transmit HDLC2 Controller End of Transmission (TxEOT) Inter-
rupt Status
This Reset-Upon-Read bit indicates whether or not the Transmit
HDLC2 Controller End of Transmission (TxEOT) Interrupt has
occurred since the last read of this register. Transmit HDLC2 Con-
troller will declare this interrupt when it has completed its transmis-
sion of a data link message. For sending large HDLC messages, it
is critical to load the next available buffer before this interrupt
occurs.
0 = Transmit HDLC2 Controller End of Transmission (TxEOT) inter-
rupt has not occurred since the last read of this register
1 = Transmit HDLC2 Controller End of Transmission (TxEOT) inter-
rupt has occurred since the last read of this register
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