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參數(shù)資料
| 型號(hào)： | XRT86VL34_07 |
| 廠商： | Exar Corporation |
| 元件分類(lèi)： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁(yè)數(shù)： | 6/175頁(yè) |
| 文件大?。?/td> | 904K |
| 代理商： | XRT86VL34_07 |
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XRT86VL34
I
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
LIST OF TABLES
T
ABLE
1: R
EGISTER
S
UMMARY
......................................................................................................................................................... 4
T
ABLE
1: C
LOCK
S
ELECT
R
EGISTER
(CSR) H
EX
A
DDRESS
: 0
XN
100 .......................... 9
T
ABLE
2: L
INE
I
NTERFACE
C
ONTROL
R
EGISTER
(LICR) H
EX
A
DDRESS
: 0
XN
101........................ 11
T
ABLE
3: F
RAMING
S
ELECT
R
EGISTER
(FSR) H
EX
A
DDRESS
: 0
XN
107 ....................... 13
T
ABLE
4: A
LARM
G
ENERATION
R
EGISTER
(AGR) H
EX
A
DDRESS
: 0
XN
108......................... 17
T
ABLE
5: S
YNCHRONIZATION
MUX R
EGISTER
(SMR) H
EX
A
DDRESS
: 0
XN
109........................ 19
T
ABLE
6: T
RANSMIT
S
IGNALING
AND
D
ATA
L
INK
S
ELECT
R
EGISTER
(TSDLSR) H
EX
A
DDRESS
:0
XN
10A ........................ 22
T
ABLE
7: F
RAMING
C
ONTROL
R
EGISTER
(FCR) H
EX
A
DDRESS
: 0
XN
10B....................... 25
T
ABLE
8: R
ECEIVE
S
IGNALING
& D
ATA
L
INK
S
ELECT
R
EGISTER
(RSDLSR) H
EX
A
DDRESS
: 0
XN
10C ....................... 27
T
ABLE
9: R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
0 (RSCR 0) H
EX
A
DDRESS
: 0
XN
10D..................... 29
T
ABLE
10: R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
1 (RSCR 1) H
EX
A
DDRESS
: 0
XN
10E .................. 29
T
ABLE
11: R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
2 (RSCR 2) H
EX
A
DDRESS
: 0
XN
10F .................. 29
T
ABLE
12: R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
3 (RSCR 3) H
EX
A
DDRESS
: 0
XN
110.................. 30
T
ABLE
13: R
ECEIVE
N
ATIONAL
B
ITS
R
EGISTER
(RNBR) H
EX
A
DDRESS
: 0
XN
111...................... 31
T
ABLE
14: R
ECEIVE
E
XTRA
B
ITS
R
EGISTER
(REBR) H
EX
A
DDRESS
: 0
XN
112..................... 32
T
ABLE
15: D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR1) H
EX
A
DDRESS
: 0
XN
113 ....................... 34
T
ABLE
16: T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR1) H
EX
A
DDRESS
: 0
XN
114..................... 36
T
ABLE
17: R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR1) H
EX
A
DDRESS
: 0
XN
115...................... 37
T
ABLE
18: S
LIP
B
UFFER
C
ONTROL
R
EGISTER
(SBCR) H
EX
A
DDRESS
: 0
XN
116...................... 38
T
ABLE
19: FIFO L
ATENCY
R
EGISTER
(FFOLR) H
EX
A
DDRESS
: 0
XN
117 ....................... 39
T
ABLE
20: DMA 0 (W
RITE
) C
ONFIGURATION
R
EGISTER
(D0WCR) H
EX
A
DDRESS
: 0
XN
118...................... 40
T
ABLE
21: DMA 1 (R
EAD
) C
ONFIGURATION
R
EGISTER
(D1RCR) H
EX
A
DDRESS
: 0
XN
119...................... 41
T
ABLE
22: I
NTERRUPT
C
ONTROL
R
EGISTER
(ICR) H
EX
A
DDRESS
: 0
XN
11A..................... 42
T
ABLE
23: LAPD S
ELECT
R
EGISTER
(LAPDSR) H
EX
A
DDRESS
: 0
XN
11B....................... 43
T
ABLE
24: P
ERFORMANCE
R
EPORT
C
ONTROL
R
EGISTER
(PRCR) H
EX
A
DDRESS
: 0
XN
11D..................... 43
T
ABLE
25: G
APPED
C
LOCK
C
ONTROL
R
EGISTER
(GCCR) H
EX
A
DDRESS
: 0
XN
11E ...................... 44
T
ABLE
26: T
RANSMIT
I
NTERFACE
C
ONTROL
R
EGISTER
(TICR) H
EX
A
DDRESS
:0
XN
120 ..................... 45
T
ABLE
27: T
RANSMIT
I
NTERFACE
S
PEED
W
HEN
M
ULTIPLEXED
M
ODE
IS
D
ISABLED
(T
X
MUXEN = 0)................................................ 47
T
ABLE
28: T
RANSMIT
I
NTERFACE
S
PEED
WHEN
M
ULTIPLEXED
M
ODE
IS
E
NABLED
(T
X
MUXEN = 1).................................................. 48
T
ABLE
29: PRBS C
ONTROL
A
ND
S
TATUS
R
EGISTER
0 (PRBSCSR0) H
EX
A
DDRESS
: 0
XN
121..................... 49
T
ABLE
30: R
ECEIVE
I
NTERFACE
C
ONTROL
R
EGISTER
(RICR) H
EX
A
DDRESS
: 0
XN
122...................... 51
T
ABLE
31: R
ECEIVE
I
NTERFACE
S
PEED
W
HEN
M
ULTIPLEXED
M
ODE
IS
D
ISABLED
(T
X
MUXEN = 0).................................................. 53
T
ABLE
32: R
ECEIVE
I
NTERFACE
S
PEED
WHEN
M
ULTIPLEXED
M
ODE
IS
E
NABLED
(T
X
MUXEN = 1).................................................... 54
T
ABLE
33: PRBS C
ONTROL
AND
S
TATUS
R
EGISTER
1 (PRBSCSR1) H
EX
A
DDRESS
: 0
XN
123 ..................... 55
T
ABLE
34: L
OOPBACK
C
ODE
C
ONTROL
R
EGISTER
(LCCR) H
EX
A
DDRESS
: 0
XN
124 ....................... 57
T
ABLE
35: T
RANSMIT
L
OOPBACK
C
ODER
R
EGISTER
(TLCR) H
EX
A
DDRESS
: 0
XN
125 ....................... 57
T
ABLE
36: R
ECEIVE
L
OOPBACK
A
CTIVATION
C
ODE
R
EGISTER
(RLACR) H
EX
A
DDRESS
: 0
XN
126..................... 57
T
ABLE
37: R
ECEIVE
L
OOPBACK
D
EACTIVATION
C
ODE
R
EGISTER
(RLDCR) H
EX
A
DDRESS
: 0
XN
127 ......................... 57
T
ABLE
38: D
EFECT
D
ETECTION
E
NABLE
R
EGISTER
(DDER) H
EX
A
DDRESS
: 0
XN
129........................ 57
T
ABLE
39: T
RANSMIT
S
A
S
ELECT
R
EGISTER
(TSASR) H
EX
A
DDRESS
: 0
XN
130....................... 58
T
ABLE
40: T
RANSMIT
S
A
A
UTO
C
ONTROL
R
EGISTER
1 (TSACR1) H
EX
A
DDRESS
: 0
XN
131....................... 60
T
ABLE
41: C
ONDITIONS
ON
R
ECEIVE
SIDE
W
HEN
TSACR1
BITS
A
RE
ENABLED
................................................................................ 61
T
ABLE
42: T
RANSMIT
S
A
A
UTO
C
ONTROL
R
EGISTER
2 (TSACR2) H
EX
A
DDRESS
: 0
XN
132.......................... 62
T
ABLE
43: C
ONDITIONS
ON
R
ECEIVE
SIDE
W
HEN
TSACR2
BITS
ENABLED
....................................................................................... 63
T
ABLE
44: T
RANSMIT
S
A
4 R
EGISTER
(TSA4R) H
EX
A
DDRESS
: 0
XN
133..................... 64
T
ABLE
45: T
RANSMIT
S
A
5 R
EGISTER
(TSA5R) H
EX
A
DDRESS
: 0
XN
134..................... 64
T
ABLE
46: T
RANSMIT
S
A
6 R
EGISTER
(TSA6R) H
EX
A
DDRESS
: 0
XN
135..................... 64
T
ABLE
47: T
RANSMIT
S
A
7 R
EGISTER
(TSA7R) H
EX
A
DDRESS
: 0
XN
136..................... 64
T
ABLE
48: T
RANSMIT
S
A
8 R
EGISTER
(TSA8R) H
EX
A
DDRESS
: 0
XN
137..................... 65
T
ABLE
49: R
ECEIVE
S
A
4 R
EGISTER
(RSA4R) H
EX
A
DDRESS
: 0
XN
13B...................... 66
T
ABLE
50: R
ECEIVE
S
A
5 R
EGISTER
(RSA5R) H
EX
A
DDRESS
: 0
XN
13C...................... 66
T
ABLE
51: R
ECEIVE
S
A
6 R
EGISTER
(RSA6R) H
EX
A
DDRESS
: 0
XN
13D...................... 66
T
ABLE
52: R
ECEIVE
S
A
7 R
EGISTER
(RSA7R) H
EX
A
DDRESS
: 0
XN
13E...................... 67
T
ABLE
53: R
ECEIVE
S
A
8 R
EGISTER
(RSA8R) H
EX
A
DDRESS
: 0
XN
13F...................... 67
T
ABLE
54: D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR2) H
EX
A
DDRESS
: 0
XN
143 ................... 68
T
ABLE
55: T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR2) H
EX
A
DDRESS
: 0
XN
144..................... 70
T
ABLE
56: R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR2) H
EX
A
DDRESS
: 0
XN
145...................... 71
T
ABLE
57: D
ATA
L
INK
C
ONTROL
R
EGISTER
(DLCR3) H
EX
A
DDRESS
: 0
XN
153 ..................... 72
T
ABLE
58: T
RANSMIT
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(TDLBCR3) H
EX
A
DDRESS
: 0
XN
154....................... 74
T
ABLE
59: R
ECEIVE
D
ATA
L
INK
B
YTE
C
OUNT
R
EGISTER
(RDLBCR3) H
EX
A
DDRESS
: 0
XN
155 ..................... 75
T
ABLE
60: D
EVICE
ID R
EGISTER
(DEVID) H
EX
A
DDRESS
: 0
XN
1FE ...................... 76
T
ABLE
61: R
EVISION
ID R
EGISTER
(REVID) H
EX
A
DDRESS
: 0
XN
1FF................... 76
T
ABLE
62: T
RANSMIT
C
HANNEL
C
ONTROL
R
EGISTER
0-31 (TCCR 0-31) H
EX
A
DDRESS
: 0X
N
300
TO
0
XN
31F...................... 77
T
ABLE
63: T
RANSMIT
U
SER
C
ODE
R
EGISTER
0 - 31 (TUCR 0-31) H
EX
A
DDRESS
: 0
XN
320
TO
0
XN
33F.................... 79
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XRT86VL34_1 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL34 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL34_2 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL34IB | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| XRT86VL38_2 | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT86VL34ES | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
| XRT86VL34IB | 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 4 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray |
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