參數(shù)資料
型號(hào): XRT86VL34_07
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù): 104/175頁(yè)
文件大?。?/td> 904K
代理商: XRT86VL34_07
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XRT86VL34
99
QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
REV. V1.2.0
T
ABLE
92: B
LOCK
I
NTERRUPT
S
TATUS
R
EGISTER
(BISR) H
EX
A
DDRESS
: 0
X
nB00
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Sa6
RO
0
Sa6 Block Interrupt Status
This bit Indicates whether or not the SA 6 block has an interrupt
request awaiting service.
0 - Indicates no outstanding SA 6 block interrupt request is awaiting
service
1 - Indicates the SA 6 block has an interrupt request awaiting ser-
vice. Interrupt Service routine should branch to the interrupt source
and read the SA6 block Interrupt Status register (address 0xnB0C)
to clear the interrupt
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the SA6 Interrupt Status Register
6
Reserved
For T1 mode only
5
RxClkLOS
RO
0
Loss of Recovered Clock Interrupt Status
This bit indicates whether or not the E1 receive framer is currently
declaring the "Loss of Recovered Clock" interrupt.
0 = Indicates that the E1 Receive Framer Block is NOT currently
declaring the "Loss of Recovered Clock" interrupt.
1 = Indicates that the E1 Receive Framer Block is currently declar-
ing the "Loss of Recovered Clock" interrupt.
N
OTE
:
This bit is only active if the clock loss detection feature is
enabled (Register - 0xn100)
4
ONESEC
RO
0
One Second Interrupt Status
This bit indicates whether or not the E1 receive framer block is cur-
rently declaring the "One Second" interrupt.
0 = Indicates that the E1 Receive Framer Block is NOT currently
declaring the "One Second" interrupt.
1 = Indicates that the E1 Receive Framer Block is currently declar-
ing the "One Second" interrupt.
3
HDLC
RO
0
HDLC Block Interrupt Status
This bit indicates whether or not the HDLC block has any interrupt
request awaiting service.
0 = Indicates no outstanding HDLC block interrupt request is await-
ing service
1 = Indicates HDLC Block has an interrupt request awaiting service.
Interrupt Service routine should branch to the interrupt source and
read the corresponding Data Link Status Registers (address
0xnB06, 0xnB16, 0xnB26, 0xnB10, 0xnB18, 0xnB28) to clear the
interrupt.
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Data Link Status
Registers that generated the interrupt.
相關(guān)PDF資料
PDF描述
XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL34IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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