參數(shù)資料
型號: XRT86VL30IV80-F
廠商: Exar Corporation
文件頁數(shù): 95/175頁
文件大?。?/td> 0K
描述: IC FRAMR/LIU T1/E1/J1 QD 80LQFP
標(biāo)準(zhǔn)包裝: 90
控制器類型: T1/E1/J1 調(diào)幀器,LIU
電源電壓: 3.3V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(12x12)
包裝: 托盤
其它名稱: 1016-1486
XRT86VL30IV80-F-ND
XRT86VL30
21
SINGLE T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. 1.0.1
4
Transmit Frame Sync
Select
R/W
0
Transmit Frame Sync Select
This bit permits the user to configure the System-Side Terminal
Equipment or the T1 Transmit Framer to dictate whenever the Trans-
mit T1 Framer block will initiate its generation and transmission of the
very next T1 frame. If the system side controls, then all of the follow-
ing will be true.
1. The corresponding TxSync_n and TxMSync_n pins will function
as input pins.
2. The Transmit T1 Framer block will initiate its generation of a new
T1 frame whenever it samples the corresponding “TxSync_n” input
pin “high” (via the TxSerClk_n input clock signal).
3. The Transmit T1 Framer block will initiate its generation of a new
Multiframe whenever it samples the corresponding “TxMSync_n”
input pin “high”.
This bit can also be used to select the direction of the transmit single
frame boundary (TxSYNC) and multi-frame boundary (TxMSYNC)
depending on whether TxSERCLK is chosen as the timing source for
the transmit section of the framer. (CSS[1:0] = 01 in register 0x0100)
If TxSERCLK is chosen as the timing source:
0 = Configures TxSYNC and TxMSYNC as inputs. (System Side
Controls)
1 = Configures TxSYNC and TxMSYNC as outputs. (Chip Controls)
If either Recovered Line Clock, MCLK PLL is chosen as the tim-
ing source:
0 = Configures TxSYNC and TxMSYNC as outputs. (Chip Controls)
1 = Configures TxSYNC and TxMSYNC as inputs. (System Side
Controls)
NOTE: TxSERCLK is chosen as the transmit clock if CSS[1:0] of the
Clock Select Register (Register Address: 0x0100) is set to
b01. Recovered Clock is chosen as the transmit clock if
CSS[1:0] is set to b00 or b11; Internal Clock is chosen as the
transmit clock if CSS[1:0] is set to b10.
3 - 2 Reserved
-
Reserved
TABLE 9: SYNCHRONIZATION MUX REGISTER (SMR)
HEX ADDRESS: 0X0109
BIT
FUNCTION
TYPE
DEFAULT
DESCRIPTION-OPERATION
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XRT86VL30IVF 制造商:Exar Corporation 功能描述:
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