參數(shù)資料
型號: XRT83VSH316IB
廠商: Exar Corporation
文件頁數(shù): 82/98頁
文件大小: 0K
描述: IC LIU SH T1/E1/J1 16CH 316STBGA
標準包裝: 60
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 16/16
規(guī)程: T1,E1,J1
電源電壓: 3.14 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 316-LBGA
供應商設備封裝: 316-STBGA(21x21)
包裝: 托盤
XRT83VSH316
80
REV. 1.0.1
16-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
D1
RLOS
Receiver Loss of Signal
The receiver loss of signal detection is always active regardless if
the interrupt generation is disabled. This bit indicates the RLOS
activity. An interrupt will not occur unless the RLOSIE is set to "1"
in the channel register 0xN04h and GIE is set to "1" in the global
register 0x0000h.
0 = No Alarm
1 = An RLOS condition is present
RO
0
D0
QRPD
Quasi Random Pattern Detection
The quasi random pattern detection is always active regardless if
the interrupt generation is disabled. This bit indicates that a QRPD
has been detected. An interrupt will not occur unless the QRPDIE
is set to "1" in the channel register 0xN04h and GIE is set to "1" in
the global register 0x0000h.
0 = No Alarm
1 = A QRP is detected
RO
0
TABLE 49: MICROPROCESSOR REGISTER 0XN06H BIT DESCRIPTION
CHANNEL N (0XN06H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
Reserved
This Bit is Reserved
RUR
0
D6
DMOIS
Digital Monitor Output Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D5
FLSIS
FIFO Limit Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D4
LCV_OFIS Line Code Violation / Overflow Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
D3
Reserved
This Bit is Reserved
RUR
0
D2
AISDIS
Alarm Indication Signal Detection Interrupt Status
0 = No change
1 = Change in status occurred
RUR
0
NOTE: The GIE bit in the global register 0x0000h must be set to "1" in addition to the individual register bits to enable the
interrupt pin.
TABLE 48: MICROPROCESSOR REGISTER 0XN05H BIT DESCRIPTION
CHANNEL N (0XN05H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
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