TABLE 41" />
參數(shù)資料
型號: XRT83SL314IB
廠商: Exar Corporation
文件頁數(shù): 63/83頁
文件大?。?/td> 0K
描述: IC LIU SH T1/E1/J1 14CH 304TBGA
標準包裝: 27
類型: 線路接口裝置(LIU)
驅動器/接收器數(shù): 14/14
規(guī)程: T1,E1,J1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 304-LBGA
供應商設備封裝: 304-TBGA(31x31)
包裝: 托盤
XRT83SL314
xr
REV. 1.0.1
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
63
TABLE 41: MICROPROCESSOR REGISTER 0XE0H BIT DESCRIPTION
GLOBAL REGISTER (0XE0H)
BIT
NAME
FUNCTION
Register
Type
Default
Value
(HW reset)
D7
SR/DR
Single Rail/Dual Rail Mode
This bit sets the LIU to receive and transmit digital data in a single
rail or a dual rail format.
0 = Dual Rail Mode
1 = Single Rail Mode
R/W
0
D6
ATAOS
Automatic Transmit All Ones
If ATAOS is selected, an all ones pattern will be transmitted on any
channel that experiences an RLOS condition. If an RLOS condi-
tion does not occur, TAOS will remain inactive.
0 = Disabled
1 = Enabled
R/W
0
D5
RCLKE
Receive Clock Data
0 = RPOS/RNEG data is updated on the rising edge of RCLK
1 = RPOS/RNEG data is updated on the falling edge of RCLK
R/W
0
D4
TCLKE
Transmit Clock Data
0 = TPOS/TNEG data is sampled on the falling edge of TCLK
1 = TPOS/TNEG data is sampled on the rising edge of TCLK
R/W
0
D3
DATAP
Data Polarity
0 = Transmit input and receive output data is active "High"
1 = Transmit input and receive output data is active "Low"
R/W
0
D2
Reserved
This Register Bit is Not Used
R/W
0
D1
GIE
Global Interrupt Enable
The global interrupt enable is used to enable/disable all interrupt
activity for all 14 channels. This bit must be set "High" for the inter-
rupt pin to operate.
0 = Disable all interrupt generation
1 = Enable interrupt generation to the individual channel registers
R/W
0
D0
SRESET
Software Reset
Writing a "1" to this bit for more than 10S initiates a device reset
for all internal circuits except the microprocessor register bits. To
reset the registers to their default setting, use the Hardware Reset
pin (See the pin description for more details).
R/W
0
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