參數(shù)資料
型號: XRT83SL216_06
廠商: Exar Corporation
英文描述: 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 16-CHANNEL素E1短途線路接口單元
文件頁數(shù): 22/42頁
文件大小: 317K
代理商: XRT83SL216_06
XRT83SL216
20
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
N
OTE
:
VDD=3.3V ±5%, T
A
=25°C, Unless Otherwise Specified
2.2
HDB3 Encoder
In single rail mode, the LIU can encode the TPOS input signal to AMI or HDB3 data. If HDB3 encoding is
selected, any sequence with four or more consecutive zeros in the input will be replaced with 000V or B00V,
where "B" indicates a pulse conforming to the bipolar rule and "V" representing a pulse violating the rule. An
example of HDB3 encoding is shown in
Table 3
.
2.3
Transmit Jitter Attenuator
The XRT83SL216 LIU is ideal for multiplexer or mapper applications where the network data crosses multiple
timing domains. As the higher data rates are de-multiplexed to E1 data, stuffing bits are typically removed
which can leave gaps in the incoming data stream. The JA can be configured in the transmit path with a 32-Bit
or 64-Bit FIFO that is used to smooth the gapped clock into a steady E1 output. The maximum gap width the
JA in the Transmit path can tolerate is shown in
Table 4
.
N
OTE
:
If the LIU is used in a loop timing system, the JA should be configured in the receive path. See the Receive Section
of this datasheet.
T
ABLE
2: T
IMING
S
PECIFICATIONS
FOR
TCLK/TPOS/TNEG
P
ARAMETER
S
YMBOL
M
IN
T
YP
M
AX
U
NITS
TCLK Duty Cycle
T
CDU
30
50
70
%
Transmit Data Setup Time
T
SU
50
-
-
ns
Transmit Data Hold Time
T
HO
30
-
-
ns
TCLK Rise Time (10% to 90%)
TCLK
R
-
-
40
ns
TCLK Fall Time (90% to 10%)
TCLK
F
-
-
40
ns
T
ABLE
3: E
XAMPLES
OF
HDB3 E
NCODING
N
UMBER
OF
P
ULSES
B
EFORE
N
EXT
4 Z
EROS
Input
0000
HDB3 (Case 1)
Odd
000V
HDB3 (Case 2)
Even
B00V
T
ABLE
4: M
AXIMUM
G
AP
W
IDTH
FOR
M
ULTIPLEXER
/M
APPER
A
PPLICATIONS
FIFO D
EPTH
M
AXIMUM
G
AP
W
IDTH
32-Bit
20 UI
64-Bit
50 UI
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