參數(shù)資料
型號: XRT83SL216_06
廠商: Exar Corporation
英文描述: 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 16-CHANNEL素E1短途線路接口單元
文件頁數(shù): 21/42頁
文件大小: 317K
代理商: XRT83SL216_06
XRT83SL216
19
REV. 1.0.0
16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
2.0
TRANSMIT PATH LINE INTERFACE
The transmit path consists of 16 independent E1 transmitters. The following section describes the complete
transmit path from TCLK/TPOS/TNEG inputs to TTIP/TRING outputs. A simplified block diagram of the
transmit path is shown in
Figure 10
.
2.1
TCLK/TPOS/TNEG Digital Inputs
In dual rail mode, TPOS and TNEG are the digital inputs for the transmit path. In single rail mode, TNEG can
be tied to ground. The XRT83SL216 can be programmed to sample the inputs on either edge of TCLK. By
default, data is sampled on the falling edge of TCLK. To sample data on the rising edge of TCLK, set TCLKinv
to "1" in the appropriate global register.
Figure 11
is a timing diagram of the transmit input data sampled on the
falling edge of TCLK.
Figure 12
is a timing diagram of the transmit input data sampled on the rising edge of
TCLK. The timing specifications are shown in
Table 2
.
F
IGURE
11. T
RANSMIT
D
ATA
S
AMPLED
ON
F
ALLING
E
DGE
OF
TCLK
F
IGURE
12. T
RANSMIT
D
ATA
S
AMPLED
ON
R
ISING
E
DGE
OF
TCLK
F
IGURE
10. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
T
RANSMIT
P
ATH
HDB3
Encoder
Tx Jitter
Attenuator
Timing
Control
Tx Pulse Shaper
Line Driver
TTIP
TRING
TCLK
TPOS
TNEG
TCLK
TPOS
or
TNEG
TCLK
R
TCLK
F
T
HO
T
SU
TCLK
TPOS
or
TNEG
TCLK
F
TCLK
R
T
HO
T
SU
相關PDF資料
PDF描述
XRT83SL216IB 16-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT
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XRT83SL30 SINGLE-CHANNEL T1/E1/J1 SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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相關代理商/技術參數(shù)
參數(shù)描述
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