參數(shù)資料
型號(hào): XRT83SH38_0609
廠商: Exar Corporation
英文描述: 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: 8通道的T1/E1/J1短途線路接口單元
文件頁數(shù): 24/78頁
文件大?。?/td> 606K
代理商: XRT83SH38_0609
XRT83SH38
21
8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.7
3.0
RECEIVE PATH LINE INTERFACE
The receive path of the XRT83SH38 LIU consists of 8 independent T1/E1/J1 receivers. The following section
describes the complete receive path from RTIP/RRING inputs to RCLK/RPOS/RNEG outputs. A simplified
block diagram of the receive path is shown in
Figure 5
.
F
IGURE
5. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
R
ECEIVE
P
ATH
3.1
Line Termination (RTIP/RRING)
3.1.1
CASE 1: Internal Termination
The input stage of the receive path accepts standard T1/E1/J1 twisted pair or E1 coaxial cable inputs through
RTIP and RRING. The physical interface is optimized by placing the terminating impedance inside the LIU.
This allows one bill of materials for all modes of operation reducing the number of external components
necessary in system design. The receive termination impedance is selected by programming TERSEL[1:0] to
match the line impedance. Selecting the internal impedance is shown in
Table 3
.
16
x
0
1
1
0
2048
16
x
0
1
1
1
1544
56
x
1
0
0
0
2048
56
x
1
0
0
1
1544
64
x
1
0
1
0
2048
64
x
1
0
1
1
1544
128
x
1
1
0
0
2048
128
x
1
1
0
1
1544
256
x
1
1
1
0
2048
256
x
1
1
1
1
1544
T
ABLE
3: S
ELECTING
THE
I
NTERNAL
I
MPEDANCE
TERSEL[1:0]
R
ECEIVE
T
ERMINATION
0h (00)
100
1h (01)
110
2h (10)
75
3h (11)
120
T
ABLE
2: M
ASTER
C
LOCK
G
ENERATOR
MCLKE1
K
H
Z
MCLKT1
K
H
Z
CLKSEL2
CLKSEL1
CLKSEL0
MCLKRATE
M
ASTER
C
LOCK
K
H
Z
HDB3/B8ZS
Decoder
Rx Jitter
Attenuator
Clock & Data
Recovery
Peak Detector
& Slicer
RTIP
RRING
RCLK
相關(guān)PDF資料
PDF描述
XRT83SH38IB 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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