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參數(shù)資料
| 型號(hào)： | XRT83SH314IB |
| 廠商： | EXAR CORP |
| 元件分類： | 數(shù)字傳輸電路 |
| 英文描述： | 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| 中文描述： | DATACOM, PCM TRANSCEIVER, PBGA304 |
| 封裝： | 31 X 31 MM, 1.27 MM PITCH, PLASTIC, BGA-304 |
| 文件頁數(shù)： | 6/101頁 |
| 文件大?。?/td> | 656K |
| 代理商： | XRT83SH314IB |
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XRT83SH314
III
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.4
F
IGURE
48. J
ITTER
T
RANSFER
F
UNCTION
- E1 TX 1.5H
Z
64
BITS
......................................................................................................... 54
F
IGURE
49. J
ITTER
T
RANSFER
F
UNCTION
- E1 RX 10H
Z
32
BITS
......................................................................................................... 55
F
IGURE
50. J
ITTER
T
RANSFER
F
UNCTION
- E1 RX 10H
Z
64
BITS
......................................................................................................... 56
F
IGURE
51. J
ITTER
T
RANSFER
F
UNCTION
- E1 RX 1.5H
Z
64
BITS
........................................................................................................ 57
4.8.2 INTRINSIC JITTER...................................................................................................................................................... 57
F
IGURE
52. T
EST
C
IRCUIT
FOR
I
NTRINSIC
J
ITTER
M
EASUREMENTS
........................................................................................................ 58
F
IGURE
53. I
NTRINSIC
J
ITTER
- T1 M
AX
.
VALUE
MEASURED
.019UI
PP
.................................................................................................. 58
F
IGURE
54. E1 I
NTRINSIC
J
ITTER
- M
AX
.
VALUE
MEASURED
.023UI
PP
.................................................................................................. 59
4.8.3 JITTER TRANSFER CURVE ...................................................................................................................................... 59
F
IGURE
55. T
EST
C
IRCUIT
FOR
J
ITTER
T
RANSFER
C
URVE
..................................................................................................................... 59
5.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................60
T
ABLE
14: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
.......................................................................................................... 60
F
IGURE
56. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
........................................................................ 60
5.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 61
T
ABLE
15: XRT84SH314S M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
COMMON
TO
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
.......................... 61
T
ABLE
16: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................................................... 61
T
ABLE
17: M
OTOROLA
M
ODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
................................................................................................. 62
5.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 63
F
IGURE
57. I
NTEL
μP I
NTERFACE
T
IMING
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
W
HEN
ALE I
S
N
OT
T
IED
’HIGH’ ... 64
T
ABLE
18: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
.............................................................................................. 64
F
IGURE
58. I
NTEL
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
W
ITH
ALE HI
GH
......................... 65
T
ABLE
19: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
.............................................................................................. 65
5.3 MPC86X MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ............................................................. 66
F
IGURE
59. M
OTOROLA
MPC86X μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.......................... 67
T
ABLE
20: M
OTOROLA
MPC86X M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
...................................................................... 67
F
IGURE
60. M
OTOROLA
68K μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................................. 68
T
ABLE
21: M
OTOROLA
68K M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
.............................................................................. 68
6.0 REGISTER DESCRIPTIONS ................................................................................................................69
6.1 REGISTER LISTS ........................................................................................................................................... 69
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
(ADDR[7:0]).......................................................................................................... 69
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
C
HANNEL
D
ESCRIPTION
.......................................................................................................... 69
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
G
LOBAL
D
ESCRIPTION
............................................................................................................ 70
6.2 DETAIL BIT DESCRIPTIONS ......................................................................................................................... 71
T
ABLE
25: M
ICROPROCESSOR
R
EGISTER
0
X
00
H
B
IT
D
ESCRIPTION
........................................................................................................ 71
T
ABLE
26: C
ABLE
L
ENGTH
C
ONTROL
.................................................................................................................................................... 72
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
........................................................................................................ 73
T
ABLE
28: M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
........................................................................................................ 74
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
........................................................................................................ 74
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
........................................................................................................ 75
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
........................................................................................................ 76
T
ABLE
33: M
ICROPROCESSOR
R
EGISTER
0
X
07
H
B
IT
D
ESCRIPTION
........................................................................................................ 78
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
0
X
06
H
B
IT
D
ESCRIPTION
........................................................................................................ 78
T
ABLE
34: M
ICROPROCESSOR
R
EGISTER
0
X
08
H
B
IT
D
ESCRIPTION
........................................................................................................ 79
T
ABLE
35: M
ICROPROCESSOR
R
EGISTER
0
X
09
H
B
IT
D
ESCRIPTION
........................................................................................................ 79
T
ABLE
36: M
ICROPROCESSOR
R
EGISTER
0
X
0A
H
B
IT
D
ESCRIPTION
....................................................................................................... 79
T
ABLE
37: M
ICROPROCESSOR
R
EGISTER
0
X
0B
H
B
IT
D
ESCRIPTION
....................................................................................................... 79
T
ABLE
38: M
ICROPROCESSOR
R
EGISTER
0
X
0C
H
B
IT
D
ESCRIPTION
....................................................................................................... 80
T
ABLE
39: M
ICROPROCESSOR
R
EGISTER
0
X
0D
H
B
IT
D
ESCRIPTION
....................................................................................................... 80
T
ABLE
40: M
ICROPROCESSOR
R
EGISTER
0
X
0E
H
B
IT
D
ESCRIPTION
....................................................................................................... 80
T
ABLE
41: M
ICROPROCESSOR
R
EGISTER
0
X
0F
H
B
IT
D
ESCRIPTION
........................................................................................................ 80
T
ABLE
42: M
ICROPROCESSOR
R
EGISTER
0
X
E0
H
B
IT
D
ESCRIPTION
....................................................................................................... 81
T
ABLE
43: M
ICROPROCESSOR
R
EGISTER
0
X
E1
H
B
IT
D
ESCRIPTION
....................................................................................................... 82
T
ABLE
44: M
ICROPROCESSOR
R
EGISTER
0
X
E2
H
B
IT
D
ESCRIPTION
....................................................................................................... 82
T
ABLE
45: M
ICROPROCESSOR
R
EGISTER
0
X
E3
H
B
IT
D
ESCRIPTION
....................................................................................................... 83
T
ABLE
46: M
ICROPROCESSOR
R
EGISTER
0
X
E4
H
B
IT
D
ESCRIPTION
....................................................................................................... 83
T
ABLE
47: M
ICROPROCESSOR
R
EGISTER
0
X
E5
H
B
IT
D
ESCRIPTION
....................................................................................................... 84
T
ABLE
48: M
ICROPROCESSOR
R
EGISTER
0
X
E6
H
B
IT
D
ESCRIPTION
....................................................................................................... 85
T
ABLE
49: M
ICROPROCESSOR
R
EGISTER
0
X
E7
H
B
IT
D
ESCRIPTION
....................................................................................................... 86
T
ABLE
50: M
ICROPROCESSOR
R
EGISTER
0
X
E8
H
B
IT
D
ESCRIPTION
....................................................................................................... 86
6.2.1 CLOCK SELECT REGISTER...................................................................................................................................... 87
F
IGURE
61. R
EGISTER
0
X
E9
H
S
UB
R
EGISTERS
..................................................................................................................................... 87
T
ABLE
51: M
ICROPROCESSOR
R
EGISTER
0
X
E9
H
B
IT
D
ESCRIPTION
....................................................................................................... 88
T
ABLE
52: M
ICROPROCESSOR
R
EGISTER
0
X
EA
H
B
IT
D
ESCRIPTION
....................................................................................................... 89
T
ABLE
53: M
ICROPROCESSOR
R
EGISTER
0
X
EB
H
B
IT
D
ESCRIPTION
....................................................................................................... 89
T
ABLE
54: E1 A
RBITRARY
S
ELECT
........................................................................................................................................................ 90
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRT83SH314IB-F | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:BGA-59 |
| XRT83SH314IB-SAK | 制造商:Exar Corporation 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT 制造商:EXAR 功能描述:14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38_0609 | 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT |
| XRT83SH38ES | 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 8 CHT1/E1LIUSH RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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