參數(shù)資料
型號(hào): XRT83SH314IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
中文描述: DATACOM, PCM TRANSCEIVER, PBGA304
封裝: 31 X 31 MM, 1.27 MM PITCH, PLASTIC, BGA-304
文件頁(yè)數(shù): 22/101頁(yè)
文件大?。?/td> 656K
代理商: XRT83SH314IB
XRT83SH314
18
14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.4
2.2
Clock and Data Recovery
The receive clock (RCLK) is recovered by the clock and data recovery circuitry. An internal PLL locks on the
incoming data stream and outputs a clock that’s in phase with the incoming signal. This allows for multi-
channel T1/E1/J1 signals to arrive from different timing sources and remain independent. In the absence of an
incoming signal, RCLK maintains its timing by using the internal master clock as its reference. The recovered
data can be updated on either edge of RCLK. By default, data is updated on the rising edge of RCLK. To
update data on the falling edge of RCLK, set RCLKE to "1" in the appropriate global register.
Figure 6
is a
timing diagram of the receive data updated on the rising edge of RCLK.
Figure 7
is a timing diagram of the
receive data updated on the falling edge of RCLK. The timing specifications are shown in
Table 4
.
F
IGURE
6. R
ECEIVE
D
ATA
U
PDATED
ON
THE
R
ISING
E
DGE
OF
RCLK
F
IGURE
7. R
ECEIVE
D
ATA
U
PDATED
ON
THE
F
ALLING
E
DGE
OF
RCLK
RCLK
RPOS
or
RNEG
R
DY
RCLK
R
RCLK
F
R
OH
RCLK
RPOS
or
RNEG
R
DY
RCLK
F
RCLK
R
R
OH
相關(guān)PDF資料
PDF描述
XRT83SH38 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH38_0609 8-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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