參數(shù)資料
型號： XRT83L314
廠商： Exar Corporation
英文描述： 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述： 14-CHANNEL的T1/E1/J1 LONG-HAUL/SHORT-HAUL線路接口單元
文件頁數(shù)： 6/84頁
文件大?。?/td> 631K
代理商： XRT83L314
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
III
F
IGURE
40. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
A
N
ON
-I
NTRUSIVE
M
ONITORING
A
PPLICATION
..................................................................... 41
5.0 MICROPROCESSOR INTERFACE BLOCK ........................................................................................42
T
ABLE
14: S
ELECTING
THE
M
ICROPROCESSOR
I
NTERFACE
M
ODE
.......................................................................................................... 42
F
IGURE
41. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
M
ICROPROCESSOR
I
NTERFACE
B
LOCK
........................................................................ 42
5.1 THE MICROPROCESSOR INTERFACE BLOCK SIGNALS ......................................................................... 43
T
ABLE
15: XRT84L314 M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
THAT
EXHIBIT
CONSTANT
ROLES
IN
BOTH
I
NTEL
AND
M
OTOROLA
M
ODES
43
T
ABLE
16: I
NTEL
MODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
........................................................................................................... 43
T
ABLE
17: M
OTOROLA
M
ODE
: M
ICROPROCESSOR
I
NTERFACE
S
IGNALS
................................................................................................. 44
5.2 INTEL MODE PROGRAMMED I/O ACCESS (ASYNCHRONOUS) ............................................................... 45
F
IGURE
42. I
NTEL
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................................................. 46
T
ABLE
18: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
.............................................................................................. 46
5.3 MOTOROLA MODE PROGRAMMED I/O ACCESS (SYNCHRONOUS) ....................................................... 47
F
IGURE
43. M
OTOROLA
μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.......................................... 48
T
ABLE
19: I
NTEL
M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
.............................................................................................. 48
F
IGURE
44. M
OTOROLA
68K μP I
NTERFACE
S
IGNALS
D
URING
P
ROGRAMMED
I/O R
EAD
AND
W
RITE
O
PERATIONS
.................................. 49
T
ABLE
20: M
OTOROLA
68K M
ICROPROCESSOR
I
NTERFACE
T
IMING
S
PECIFICATIONS
.............................................................................. 49
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
A
DDRESS
(ADDR[7:0]).......................................................................................................... 50
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
C
HANNEL
D
ESCRIPTION
.......................................................................................................... 50
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
G
LOBAL
D
ESCRIPTION
............................................................................................................ 51
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
0
X
00
H
B
IT
D
ESCRIPTION
........................................................................................................ 52
T
ABLE
25: E
QUALIZER
C
ONTROL
AND
T
RANSMIT
L
INE
B
UILD
O
UT
.......................................................................................................... 52
T
ABLE
26: M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
........................................................................................................ 54
T
ABLE
27: M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
........................................................................................................ 55
T
ABLE
28: M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
........................................................................................................ 56
T
ABLE
29: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
........................................................................................................ 57
T
ABLE
30: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
........................................................................................................ 58
T
ABLE
31: M
ICROPROCESSOR
R
EGISTER
0
X
06
H
B
IT
D
ESCRIPTION
........................................................................................................ 59
T
ABLE
32: M
ICROPROCESSOR
R
EGISTER
0
X
07
H
B
IT
D
ESCRIPTION
........................................................................................................ 60
T
ABLE
33: M
ICROPROCESSOR
R
EGISTER
0
X
08
H
B
IT
D
ESCRIPTION
........................................................................................................ 61
T
ABLE
34: M
ICROPROCESSOR
R
EGISTER
0
X
09
H
B
IT
D
ESCRIPTION
........................................................................................................ 61
T
ABLE
35: M
ICROPROCESSOR
R
EGISTER
0
X
0A
H
B
IT
D
ESCRIPTION
....................................................................................................... 61
T
ABLE
36: M
ICROPROCESSOR
R
EGISTER
0
X
0B
H
B
IT
D
ESCRIPTION
....................................................................................................... 62
T
ABLE
37: M
ICROPROCESSOR
R
EGISTER
0
X
0C
H
B
IT
D
ESCRIPTION
....................................................................................................... 62
T
ABLE
38: M
ICROPROCESSOR
R
EGISTER
0
X
0D
H
B
IT
D
ESCRIPTION
....................................................................................................... 62
T
ABLE
39: M
ICROPROCESSOR
R
EGISTER
0
X
0E
H
B
IT
D
ESCRIPTION
....................................................................................................... 62
T
ABLE
40: M
ICROPROCESSOR
R
EGISTER
0
X
0F
H
B
IT
D
ESCRIPTION
........................................................................................................ 63
T
ABLE
41: M
ICROPROCESSOR
R
EGISTER
0
X
E0
H
B
IT
D
ESCRIPTION
....................................................................................................... 63
T
ABLE
42: M
ICROPROCESSOR
R
EGISTER
0
X
E1
H
B
IT
D
ESCRIPTION
....................................................................................................... 64
T
ABLE
43: M
ICROPROCESSOR
R
EGISTER
0
X
E2
H
B
IT
D
ESCRIPTION
....................................................................................................... 65
T
ABLE
44: M
ICROPROCESSOR
R
EGISTER
0
X
E3
H
B
IT
D
ESCRIPTION
....................................................................................................... 65
T
ABLE
45: M
ICROPROCESSOR
R
EGISTER
0
X
E4
H
B
IT
D
ESCRIPTION
....................................................................................................... 66
T
ABLE
46: M
ICROPROCESSOR
R
EGISTER
0
X
E5
H
B
IT
D
ESCRIPTION
....................................................................................................... 67
T
ABLE
47: M
ICROPROCESSOR
R
EGISTER
0
X
E6
H
B
IT
D
ESCRIPTION
....................................................................................................... 68
T
ABLE
48: M
ICROPROCESSOR
R
EGISTER
0
X
E7
H
B
IT
D
ESCRIPTION
....................................................................................................... 69
T
ABLE
49: M
ICROPROCESSOR
R
EGISTER
0
X
E8
H
B
IT
D
ESCRIPTION
....................................................................................................... 69
CLOCK SELECT REGISTER ....................................................................................................... 70
F
IGURE
45. R
EGISTER
0
X
E9
H
S
UB
R
EGISTERS
..................................................................................................................................... 70
T
ABLE
50: M
ICROPROCESSOR
R
EGISTER
0
X
E9
H
B
IT
D
ESCRIPTION
....................................................................................................... 70
T
ABLE
51: M
ICROPROCESSOR
R
EGISTER
0
X
EA
H
B
IT
D
ESCRIPTION
....................................................................................................... 72
T
ABLE
52: M
ICROPROCESSOR
R
EGISTER
0
X
EB
H
B
IT
D
ESCRIPTION
....................................................................................................... 72
T
ABLE
53: E1 A
RBITRARY
S
ELECT
........................................................................................................................................................ 73
T
ABLE
54: M
ICROPROCESSOR
R
EGISTER
0
X
FE
H
B
IT
D
ESCRIPTION
....................................................................................................... 74
T
ABLE
55: M
ICROPROCESSOR
R
EGISTER
0
X
FF
H
B
IT
D
ESCRIPTION
....................................................................................................... 74
T
ABLE
56: A
BSOLUTE
M
AXIMUM
R
ATINGS
............................................................................................................................................. 75
T
ABLE
57: DC D
IGITAL
I
NPUT
AND
O
UTPUT
E
LECTRICAL
C
HARACTERISTICS
........................................................................................... 75
T
ABLE
58: AC E
LECTRICAL
C
HARACTERISTICS
...................................................................................................................................... 75
T
ABLE
59: P
OWER
C
ONSUMPTION
........................................................................................................................................................ 76
T
ABLE
60: E1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
...................................................................................................................... 76
T
ABLE
61: T1 R
ECEIVER
E
LECTRICAL
C
HARACTERISTICS
...................................................................................................................... 77
T
ABLE
62: E1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
................................................................................................................. 78
T
ABLE
63: T1 T
RANSMITTER
E
LECTRICAL
C
HARACTERISTICS
................................................................................................................. 78
ORDERING INFORMATION......................................................................................................... 79
PACKAGE DIMENSIONS (DIE DOWN) ....................................................................................... 79
R
EVISION
H
ISTORY
......................................................................................................................................................80
相關(guān)PDF資料
PDF描述
XRT83L314IB 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
XRT83L34 QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83L34IV QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
XRT83SH314 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
XRT83SH314_0610 14-CHANNEL T1/E1/J1 SHORT-HAUL LINE INTERFACE UNIT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT83L314ES 功能描述:LIN 收發(fā)器 RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT83L314IB 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT83L314IB-F 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT83L314IB-L 功能描述:LIN 收發(fā)器 14 channel, LH/SH T1/E1 LIU RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT83L34 制造商:EXAR 制造商全稱:EXAR 功能描述:QUAD T1/E1/J1 LH/SH TRANSCEIVER WITH CLOCK RECOVERY AND JITTER ATTENUATOR
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