參數(shù)資料
型號(hào): XRT83L314
廠商: Exar Corporation
英文描述: 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
中文描述: 14-CHANNEL的T1/E1/J1 LONG-HAUL/SHORT-HAUL線路接口單元
文件頁(yè)數(shù): 49/84頁(yè)
文件大?。?/td> 631K
代理商: XRT83L314
XRT83L314
14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
REV. 1.0.0
45
5.2
If the LIU is interfaced to an Intel type μP, then it should be configured to operate in the Intel mode. Intel type
Read and Write operations are described below.
Intel Mode Read Cycle
Whenever an Intel-type μP wishes to read the contents of a register, it should do the following.
1.
Place the address of the target register on the address bus input pins ADDR[10:0].
2.
While the μP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
μP and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The μP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
Next, the μP should indicate that this current bus cycle is a Read operation by toggling the RD input pin
"Low". This action also enables the bi-directional data bus output drivers of the LIU.
6.
After the μP toggles the Read signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the μP that the data is available to be read by the μP, and that it is ready for the next com-
mand.
7.
After the μP detects the RDY signal and has read the data, it can terminate the Read Cycle by toggling the
RD input pin "High".
N
OTE
:
ALE
can be tied “High” if this signal is not available.
The Intel Mode Write Cycle
Whenever an Intel type μP wishes to write a byte or word of data into a register within the LIU, it should do the
following.
1.
Place the address of the target register on the address bus input pins ADDR[10:0].
2.
While the μP is placing this address value on the address bus, the address decoding circuitry should
assert the CS pin of the LIU, by toggling it "Low". This action enables further communication between the
μP and the LIU microprocessor interface block.
3.
Toggle the ALE input pin "High". This step enables the address bus input drivers, within the microproces-
sor interface block of the LIU.
4.
The μP should then toggle the ALE pin "Low". This step causes the LIU to latch the contents of the address
bus into its internal circuitry. At this point, the address of the register has now been selected.
5.
The μP should then place the byte or word that it intends to write into the target register, on the bi-direc-
tional data bus DATA[7:0].
6.
Next, the μP should indicate that this current bus cycle is a Write operation by toggling the
WR
input pin
"Low". This action also enables the bi-directional data bus input drivers of the LIU.
7.
After the μP toggles the Write signal "Low", the LIU will toggle the RDY output pin "Low". The LIU does this
in order to inform the μP that the data has been written into the internal register location, and that it is ready
for the next command.
N
OTE
:
ALE
can be tied “High” if this signal is not available.
The Intel Read and Write timing diagram is shown in Figure 42. The timing specifications are shown in
Table 18.
I
NTEL
M
ODE
P
ROGRAMMED
I/O A
CCESS
(A
SYNCHRONOUS
)
相關(guān)PDF資料
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XRT83L314IB 14-CHANNEL T1/E1/J1 LONG-HAUL/SHORT-HAUL LINE INTERFACE UNIT
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