REV. 1.0.3 5 CONTROL FUNCTION PIN
參數(shù)資料
型號: XRT83D10IW
廠商: Exar Corporation
文件頁數(shù): 14/18頁
文件大小: 0K
描述: IC LIU T1/E1 SGL 28SOJ
標(biāo)準(zhǔn)包裝: 27
類型: 線路接口裝置(LIU)
驅(qū)動器/接收器數(shù): 1/1
規(guī)程: T1,E1
電源電壓: 3.135 V ~ 3.465 V
安裝類型: 表面貼裝
封裝/外殼: 28-BSOJ
供應(yīng)商設(shè)備封裝: 28-SOJ
包裝: 管件
xr
XRT83D10
SINGLE CHANNEL DS1/CEPT LINE INTERFACE UNIT
REV. 1.0.3
5
CONTROL FUNCTION
PIN #NAME
TYPE
DESCRIPTION
2ICT
I
In Circuit Testing
When this pin is tied "Low" all output pins are forced to high-impedance state
for in-circuit testing.
NOTE: Internally pulled up.
16
ExCLK
I
External Clock Input:
DS1 (1.544 MHz ± 130 ppm) or CEPT E1 (2.048 MHz ± 80 ppm) clock signal is
provided. ExCLK must be an independent clock to guarantee device perfor-
mance for all specifications. This clock must be continuously active (ungapped
or unswitched) and void of jitter for the device to operate properly.
11
TAOS
I
Transmit All Ones:
With this pin tied "High", an AMI encoded all "1’s" signal sent to the transmit
output using ExCLK as the timing reference. A remote loop back has higher
priority over TAOS request.
NOTE: Internally pulled down.
9LOOPB
I
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
NOTE: Internally Pulled down.
10
LOOPA
I
Loopback control.
LOOPB along with LOOPA is used for selecting different loopbacks.
NOTE: Internally Pulled down.
13
FOFS
O
FIFO Overflow Signal:
This pin is set "High" if the phase jitter of the incoming signal exceeds the toler-
ance of the jitter attenuator’s buffer. This may result in loss of data and Jitter
Attenuator is no longer attenuating jitter.
POWER AND GROUND
PIN #NAME
TYPE
DESCRIPTION
3
AVDD
****
Analog Supply: 5V ± 5% or 3.3V ± 5%
4
AGND
****
Analog GND.
24
DVDD
****
Digital Supply: 5V ± 5% or 3.3V ± 5%
26
DGND
****
Digital GND
LOOPA
0
Loopback Mode
Normal Operation
Digital
LOOPB
0
1
Remote
Local
0
1
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