
XRT82D20
SINGLE CHANNEL E1 LINE INTERFACE UNIT
á
REV. 1.0.6
I
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES ................................................................................................................................................ 1
APPLICATIONS ......................................................................................................................................... 1
Figure 1. Block Diagram of the XRT82D20 .................................................................................................. 1
Figure 2. Pinout of the XRT82D20 ................................................................................................................ 2
O
RDERING
I
NFORMATION
.............................................................................................................................. 2
PIN DESCRIPTIONS .......................................................................................................... 3
Figure 3. Interface Timing Diagram in Both Single-Rail and Dual-Rail Mode, with DIGI (Pin 17) = “0” . 5
Figure 4. Interface Timing Diagram in Dual-Rail Mode only, with DIGI (Pin 17) = “1” ............................. 6
ELECTRICAL CHARACTERISTICS .................................................................................. 7
T
ABLE
1: R
ECEIVER
C
HARACTERISTICS
(TA = 25°C, VDD = 3.3V± 5%
OR
5V± 5% U
NLESS
OTHERWISE
SPECIFIED
)
............................................................................................................................................................................7
T
ABLE
2: T
RANSMITTER
C
HARACTERISTICS
: (TA = 25°C, VDD = 3.3V± 5%
OR
5V± 5% U
NLESS
OTHERWISE
SPEC
-
IFIED
) .................................................................................................................................................................. 7
T
ABLE
3: P
OWER
C
ONSUMPTION
INCLUDING
THE
L
INE
P
OWER
D
ISSIPATION
, T
RANSMISSION
AND
RECEIVE
P
ATHS
ALL
A
CTIVE
(TA = -40°
TO
85°C, VDD = 3.3V± 5% U
NLESS
OTHERWISE
SPECIFIED
) ................................................. 7
T
ABLE
4: P
OWER
C
ONSUMPTION
INCLUDING
THE
L
INE
P
OWER
D
ISSIPATION
, T
RANSMISSION
AND
RECEIVE
P
ATHS
ALL
A
CTIVE
(TA = -40°
TO
85°C, VDD = 5V ± 5% U
NLESS
OTHERWISE
SPECIFIED
) ................................................... 8
T
ABLE
5: AC E
LECTRICAL
C
HARACTERISTICS
................................................................................................... 8
T
ABLE
6: DC E
LECTRICAL
C
HARACTERISTICS
; (T
A
= 25°C, V
DD
=3.3V ± 5%
OR
5V ± 5%
UNLESS
OTHERWISE
SPEC
-
IFIED
) .................................................................................................................................................................. 9
A
BSOLUTE
MAXIMUM
R
ATINGS
.......................................................................................................... 9
Figure 5. Receiver Maximum Jitter Tolerance, Test Conditions: Test Patterrn 2^15-1, (-6dB) Cable Loss
10
Figure 6. Receiver Jitter Transfer Function (Jitter Attenuator Disabled, Test Conditions: Test Pattern
2^15-1, Input Jitter 0.5UIp-p ......................................................................................................................... 11
Figure 7. Receiver Jitter Transfer Function (Jitter Attenuator enabled) Test Conditions: Test Pattern
2^15-1, Input Jitter 75% of Maximum Jitter Tolerance .............................................................................. 11
SYSTEM DESCRIPTION .................................................................................................. 12
1.0 THE Receive Section ........................................................................................................................ 12
1.1 JITTER ATTENUATOR .................................................................................................................................. 12
1.2 THE TRANSMIT SECTION ............................................................................................................................ 12
Figure 8. Illustration on how the XRT82D20 Samples the data on the TPOS and TNEG input pins .... 12
1.3 T
HE
P
ULSE
S
HAPING
C
IRCUIT
........................................................................................................................... 12
Figure 9. Illustration of the ITU-T G.703 Pulse Template for E1 Application .......................................... 13
1.4 I
NTERFACING
THE
T
RANSMIT
S
ECTION
OF
THE
XRT82D20
TO
THE
L
INE
............................................................. 13
Figure 10. Illustration of how to interface the XRT82D20 to the Line for 75 W Applications and 3.3V op-
eration only .................................................................................................................................................... 14
Figure 11. Illustration of how to interface the XRT82D20 to the Line for 120 W Applications and 3.3V op-
eration only .................................................................................................................................................... 15
1.5 I
NTERFACING
THE
R
ECEIVE
S
ECTION
TO
THE
L
INE
............................................................................................. 15
Figure 12. Recommended Schematic for Transformer-Coupling the XRT82D20 to the Line for 75 W Ap-
plications and 5 V operation only ................................................................................................................ 16
Figure 13. Recommended Schematic for Transformer-Coupling the XRT82D20 to the Line for 120 W Ap-
plications and 5 V operation only ................................................................................................................ 17
2.0 Diagnostic Features ......................................................................................................................... 17
2.1 T
HE
L
OCAL
L
OOP
-B
ACK
M
ODE
......................................................................................................................... 17
Figure 14. Illustration of the Analog Local Loop-Back within the XRT82D20 ........................................ 18
2.2 T
HE
R
EMOTE
L
OOP
B
ACK
M
ODE
....................................................................................................................... 18
Figure 15. Illustration of the Remote Loop-Back path, within the XRT82D20 ........................................ 19
PACKAGE OUTLINE DRAWING ..................................................................................... 20
.R
EVISION
H
ISTORY
.................................................................................................................................... 21