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參數(shù)資料
| 型號： | XRT8000ID |
| 廠商： | EXAR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Clock Synchronizer/Adapter for Communications |
| 中文描述： | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO18 |
| 封裝： | 0.300 INCH, SOIC-18 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大?。?/td> | 513K |
| 代理商： | XRT8000ID |
XRT8000
15
Rev. 1.11
Using the Serial Interface
The following instructions, for using the serial interface,
are best understood by referring to the diagram in
Figure 4.
In order to use the serial interface the user must first
provide a clock signal to the SCLK input pin. Afterwards,
the user will initiates a “Read” or “Write” operation by
asserting the active low Chip Select Input pin (CSB). It is
important to note that the user assert CSB low coincident
with the falling edge of SCLK.
Once the CSB input has been asserted the type of
operation and the target register address must be
provided by the user. The user will provide this
informationtotheserialinterfacebywritingfourserialbits
of data to the SDI input. Note: Each of these bits will be
“clocked” into the SDI input, on the rising edge of SCLK.
These four bits are identified and described below.
Bit 1: The R/W (Read/Write) Bit
ThisbitwillbeclockedintotheSDIinput,onthefirstrising
edge of SCLK (after CSB has been asserted). This bit
indicateswhetherthecurrentoperationisareadorawrite
operation. A “1” in this bit will cause a “Read” operation;
whereas a “0” in this bit will cause a “Write” operation.
Bits 2 through 4: The three (3) bit address value (A0,
A1, A2)
These next three rising edges of the SCLK signal will
clock in the 3-bit address value for this particular read (or
write) operation. This address selects the command
registerwithinXRT8000devicethattheuserwilleitherbe
reading data from, or writing data to. The user must
supply the address bits to the SDI input pin, in ascending
order with the LSB first. (A3 to A5 must be low A6 is a
“don’t care”).
Once the “Read/Write” and Address bits have been
written,thesubsequentactiondependsuponwhetherthe
current operation is a “Read” or “Write” operation.
Read Operation
Once the last address bit (A2) has been clocked into the
SDI input, the read operation will proceed through an idle
period, lasting four SCLK periods. On the falling edge of
SCLK Cycle “8” (See Figure 4) the serial output signal
(SDO) becomes active. At this point the user can begin
reading the data contents of the addressed command
register (at Address A2, A1, A0) via the SDO pin. The
SDOpinwilloutputthisfive bitdataword(D0 throughD4)
in ascending order, with the LSB first, on the rising edges
of the SCLK pin.
Write Operation
Once the last address bit (A2) has been clocked into the
SDI input, thewrite operationwillproceedthrough anidle
period,lastingfourSCLKperiods. Priortotherisingedge
of SCLK Cycle #9 (See Figure 4) the user must begin to
apply the eight-bit data word, that he/she wishes to write
to the serial input interface onto the SDI input pin. The
microprocessorserialinterfacewillcatchthevalueonthe
SDI pin on the rising edge of the SCLK. The user must
apply this word (D0 through D7), serially, in ascending
order with the LSB first.
Simplified Interface Option
The user can simplify the design of the circuitry
connecting to the serial interface by tying both the SDO
and SDI pins together, and reading data from and/or
writing data to this “combined” signal. This simplification
ispossiblebecauseonlyoneofthesesignalsareactiveat
any given time. The inactive signal will be tri-stated.
Notes:
1. Prior toreading data from(or writingdatato)the SerialInter-
face, the user is not required to provide a clock signal at the
SCLK. However,shortlybeforeperforminganyreadorwrite
operationswiththeSerialInterface,theusermustsupplythe
clock signal to the SCLK input pin.
2. Each Read or Write operation, with the Serial Interface, will
require 16 SCLK periods, as depicted in Figure 4.
3. Uponcompletionofa ReadorWritecycle,theuser mustne-
gate CSBforatleast250ns(seetimingparameterT29inthe
AC Characteristics), before asserting it again for the next
Read or Write operation.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T8000ID | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Miscellaneous Clock Generator |
| XRT8000ID-F | 功能描述:時(shí)鐘合成器/抖動清除器 3.3V-5V 0.05UI temp -45 to 85C RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT8000IDTR-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8000IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000IP-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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