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參數(shù)資料
| 型號(hào)： | XRT8000ID |
| 廠商： | EXAR CORP |
| 元件分類： | XO, clock |
| 英文描述： | Clock Synchronizer/Adapter for Communications |
| 中文描述： | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO18 |
| 封裝： | 0.300 INCH, SOIC-18 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 513K |
| 代理商： | XRT8000ID |
XRT8000
14
Rev. 1.11
CR5 Register (Power On State = “00000”)
D0 : ( PL1/8) :
Select the divider by 8 for PLL1,
PL1/8 = “1” CLK1 output frequency is divided by 8.
PL1/8 = “0” CLK1 output frequency is as per table 4.
D1 : ( PL2/8) :
Select the divider by 8 for PLL2,
PL2/8 = “1” CLK2 output frequency is divided by 8.
PL2/8 = “0” CLK2 output frequency is as per table 5.
D2 : ( CLK2EN) , PLL2:
Output enable bit,
CLK2EN = “1” CLK2 output is enabled.
CLK2EN = “0” CLK2 output is Tri State D.
D3 : ( CLK1EN) , PLL1:
Output enable bit,
CLK1EN = “1” CLK1 output is enabled.
CLK1EN = “0” CLK1 output is Tri State D.
D4 : ( SYNCEN) , 8kHz SYNC enable bit:
SYNCEN = “1” SYNC output is enabled.
SYNCEN = “0” SYNC output is Tri State D.
CR6 to CR7 Register
Register reserved for future use.
Address
Data In
Data Out
R/W
A0
A1
A2
A3
A4
A5
A6
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
HiZ
HiZ
SDO
SDI
SCLK
CSB
Figure 4. Serial Processor Interface Data Structure
Note
:
A3, A4 and A5 always Low.
A6 Do not care.
R/W bit = 1 for a read operation
2 for a write operation
D5, D6 and D7 always Low
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SERIAL INTERFACE
The serial interface is a simple four wire interface that is
compatible with many of the microcontrollers available in
the market.
This interface consists of the following
signals:
CSB
SCLK
SDI
SDO
Chip Select (Active Low)
Serial Clock Input
Serial Data Input
Serial Data Output
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PDF描述 |
|---|---|
| XRT8000 | Clock Synchronizer/Adapter for Communications(用于通訊的時(shí)鐘同步設(shè)備/調(diào)整器) |
| XRT8001 | WAN Clock for T1 and E1 Systems |
| XRT8001ID | WAN Clock for T1 and E1 Systems |
| XRT8001IP | WAN Clock for T1 and E1 Systems |
| XRT8010 | 312MHZ CLOCK & CRYSTAL MULTIPLIER WITH LVDS OUTPUTS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XR-T8000ID | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Miscellaneous Clock Generator |
| XRT8000ID-F | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 3.3V-5V 0.05UI temp -45 to 85C RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT8000IDTR-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| XRT8000IP | 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications |
| XRT8000IP-F | 功能描述:鎖相環(huán) - PLL RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
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