參數(shù)資料
型號(hào)： XRT79L74IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述： ATM NETWORK INTERFACE, PBGA456
封裝： 27 X 27 MM, 1 MM PITCH, PLASTIC, BGA-456
文件頁(yè)數(shù)： 28/70頁(yè)
文件大小： 547K
代理商： XRT79L74IB
XRT79L74
REV. P1.0.0
PRELIMINARY
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
26
M4
J22
P3
K26
RxNib1_0/
RxHDLCDat1_0
RxNib2_0/
RxHDLCDat2_0
RxNib3_0/
RxHDLCDat3_0
RxNib4_0/
RxHDLCDat4_0
O
O
O
O
Receive Nibble Interface Output pin - Bit 0/Receive HDLC Controller Data
Bus output pin - Bit 0:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the Clear-Channel/Nibble-Parallel Mode, the
High-Speed HDLC Controller Mode, or in some other mode.
Clear-Channel/Nibble-Parallel Mode - RxNib_0:
The XRT79L74 will output Received data from the remote terminal equipment
to the local terminal equipment via these pins, along with RxNibn_1 through
RxNibn_3. These particular output pins function as the LSB.
The data at these pins are updated on the rising edge of the RxClk output sig-
nals. Hence, the user’s local terminal equipment should sample these signals
upon the falling edge of RxClk.
High-Speed HDLC Controller Mode - RxHDLCDat_0:
These output pins along with RxHDLCDatn_[7:1] function as the Receive HDLC
Controller byte wide output data bus. These particular output pins function as
the LSB (Least Significant Bit) of the Receive HDLC Controller byte wide data
bus. The Receive HDLC Controller will output the contents of all HDLC frames
via this output data bus, upon the rising edge of the RxHDLCClk output signals.
Hence, the user’s local terminal equipment should be designed/configured to
sample this data upon the falling edge of the RxHDLCClk output clock signals.
N
OTE
:
These output pins are only active if the XRT79L74 is configured to
operate in the Clear-Channel/Nibble-Parallel Mode or in the High-
Speed HDLC Controller Mode. These outputs are inactive for all
remaining modes.
M5
J23
P2
L24
RxLCD1/
RxOutClk1/
RxHDLCDat1_7
RxLCD2/
RxOutClk2/
RxHDLCDat2_7
RxLCD3/
RxOutClk3/
RxHDLCDat3_7
RxLCD4/
RxOutClk4/
RxHDLCDat4_7
O
O
O
O
Receive Loss of Cell Delineation indicator/Receive Output Clock signal/
Receive HDLC Controller Data Bus - Bit 7 Output:
The function of these output pins depend upon whether the XRT79L74 has
been configured to operate in the ATM, Clear-Channel Framer or High Speed
HDLC Controller Mode.
ATM Mode - RxLCD (Loss of Cell Delineation Defect Indicator)
The XRT79L74 device will assert this output pin (e.g., toggle it "high") anytime
(and for the duration that) the Receive ATM Cell Processor block is declaring
the LCD (Loss of Cell Delineation) defect condition. The XRT79L74 device will
negate this output pin (e.g., toggle it "low") whenever the Receive ATM Cell Pro-
cessor block is not currently declaring the LCD defect condition.
Clear-Channel Framer Mode - RxOutClk:
These clock signals function as the Transmit Payload Data Input Interface clock
source, if the XRT79L74 has been configured to operate in the loop-timing
mode.
In this mode, the local terminal equipment is expected to input data to the TxSer
input pins, upon the rising edge of these clock signals. The XRT79L74 will use
the rising edge of these signals to sample the data on the TxSer inputs.
High-Speed HDLC Controller Mode - RxHDLCDat_7:
These output pins along with RxHDLCDatn_[6:0] functions as the Receive
HDLC Controller byte wide output data bus. These particular output pins func-
tion as the MSB (Most Significant Bit) of the Receive HDLC Controller byte wide
data bus. The Receive HDLC Controller will output the contents of all HDLC
frames via this output data bus, upon the rising edge of the RxHDLCClk output
signals. Hence, the user’s local terminal equipment should be designed/config-
ured to sample this data upon the falling edge of the RxHDLCClk output clock
signals.
P
IN
#
N
AME
TYPE
D
ESCRIPTION
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