參數(shù)資料
型號(hào)： XRT79L74
廠商： Exar Corporation
英文描述： 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
中文描述： 4 -通道DS3/E3自動(dòng)柜員機(jī)用戶到網(wǎng)絡(luò)接口/ Combo IC對(duì)購(gòu)買力平價(jià)
文件頁(yè)數(shù)： 5/70頁(yè)
文件大?。?/td> 547K
代理商： XRT79L74
PRELIMINARY
XRT79L74
REV. P1.0.0
4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
B
TRANSMIT PAYLOAD DATA INPUT INTERFACE - TIMING REQUIREMENTS.....................................54
T
ABLE
9: T
IMING
INFORMATION
FO
RTHE
T
RNASMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
BLOCK
.......................................................... 54
F
IGURE
11. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L74
IS
OPERATING
IN
BOTH
THE
DS3
AND
L
OOP
-T
IMING
M
ODES
.............................................................................................................................................. 55
F
IGURE
12. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L74
IS
OPERATING
IN
BOTH
THE
DS3
AND
L
OCAL
-T
IMING
M
ODES
............................................................................................................................................. 56
F
IGURE
13. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L74
IS
OPERATING
IN
BOTH
THE
DS3/
N
IBBLE
-P
ARALLEL
AND
L
OOP
-T
IMING
M
ODES
.................................................................................................................. 56
F
IGURE
14. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
P
AYLOAD
D
ATA
I
NPUT
I
NTERFACE
WHEN
THE
XRT79L74
IS
OPERATING
IN
BOTH
THE
DS3/
N
IBBLE
-P
ARALLEL
AND
L
OCAL
-T
IMING
M
ODES
................................................................................................................. 57
TRANSMIT OVERHEAD DATA INPUT INTERFACE......................................................58
TRANSMIT OVERHEAD DATA INPUT INTERFACE - TIMING REQUIREMENTS..................................58
T
ABLE
10: T
IMING
I
NFORMATION
FOR
THE
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
B
LOCK
..................................................... 58
F
IGURE
15. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
(M
ETHOD
1 A
CCESS
).................................... 60
F
IGURE
16. T
IMING
D
IAGRAM
FOR
THE
T
RANSMIT
O
VERHEAD
D
ATA
I
NPUT
I
NTERFACE
(M
ETHOD
2 A
CCESS
).................................... 60
RECEIVE PAYLOAD DATA OUTPUT INTERFACE.......................................................61
RECEIVE PAYLOAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ...................................61
T
ABLE
11: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
P
AYLOAD
D
ATA
O
UTPUT
I
NTERFACE
B
LOCK
...................................................... 61
F
IGURE
17. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
P
AYLOAD
D
ATA
O
UTPUT
I
NTERFACE
(S
ERIAL
M
ODE
).............................................. 61
F
IGURE
18. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
P
AYLOAD
D
ATA
O
UTPUT
I
NTERFACE
(N
IBBLE
-P
ARALLEL
M
ODE
)............................. 62
RECEIVE OVERHEAD DATA OUTPUT INTERFACE ....................................................63
RECEIVE OVERHEAD DATA OUTPUT INTERFACE - TIMING REQUIREMENTS ................................63
AC E
LECTRICAL
C
HARACTERISTICS
(C
ONT
.).................................................................................................63
F
IGURE
19. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
O
VERHEAD
D
ATA
O
UTPUT
I
NTERFACE
(M
ETHOD
1 - U
SING
R
X
OHC
LK
).................. 64
F
IGURE
20. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
O
VERHEAD
D
ATA
O
UTPUT
I
NTERFACE
(M
ETHOD
2 - U
SING
R
X
OHE
NABLE
)............ 64
RECEIVE UTOPIA INTERFACE......................................................................................65
RECEIVE UTOPIA INTERFACE...............................................................................................................65
F
IGURE
21. T
IMING
D
IAGRAM
FOR
THE
R
ECEIVE
UTOPIA I
NTERFACE
B
LOCK
.................................................................................. 65
T
ABLE
12: T
IMING
I
NFORMATION
FOR
THE
R
ECEIVE
UTOPIA I
NTERFACE
B
LOCK
............................................................................. 65
ORDERING INFORMATION............................................................................................67
PACKAGE DIMENSIONS................................................................................................67
R
EVISION
H
ISTORY
......................................................................................................................................68
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PDF描述
XRT79L74IB 4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT79L74IB 制造商:EXAR 制造商全稱:EXAR 功能描述:4 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
XRT8000 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications
XRT8000_06 制造商:EXAR 制造商全稱:EXAR 功能描述:Clock Synchronizer/Adapter for Communications
XRT8000D 制造商:EXAR 制造商全稱:EXAR 功能描述:CLOCK SYNCHRONIZER/ADAPTER FOR COMMUNICATIONS
XRT8000ES 功能描述:鎖相環(huán) - PLL WAN CLOCK RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray
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