
XRT79L71
REV. P1.0.3
PRELIMINARY
1 - CHANNEL DS3/E3 ATM UNI/PPP COMBO IC
á
9
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - C
HECK
R
EGISTER
- B
YTE
1 (A
DDRESS
= 0
X
1778).................................................................................................................................................332
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - C
HECK
R
EGISTER
- B
YTE
2 (A
DDRESS
= 0
X
1779).................................................................................................................................................333
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - C
HECK
R
EGISTER
- B
YTE
3 (A
DDRESS
= 0
X
177A).................................................................................................................................................334
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - C
HECK
R
EGISTER
- B
YTE
4 (A
DDRESS
= 0
X
177B).................................................................................................................................................335
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - F
ILTERED
C
ELL
C
OUNT
- B
YTE
3 (A
D
-
DRESS
= 0
X
177C) .....................................................................................................................................336
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - F
ILTERED
C
ELL
C
OUNT
- B
YTE
2 (A
D
-
DRESS
= 0
X
177D) .....................................................................................................................................337
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - F
ILTERED
C
ELL
C
OUNT
- B
YTE
1 (A
D
-
DRESS
= 0
X
177E)......................................................................................................................................338
R
ECEIVE
ATM C
ELL
P
ROCESSOR
B
LOCK
- R
ECEIVE
U
SER
C
ELL
F
ILTER
# 3 - F
ILTERED
C
ELL
C
OUNT
- B
YTE
0 (A
D
-
DRESS
= 0
X
177F)......................................................................................................................................339
RECEIVE PPP PACKET PROCESSOR BLOCK (PPP APPLICATIONS ONLY)....................................340
R
ECEIVE
PPP P
ACKET
P
ROCESSOR
B
LOCK
- R
ECEIVE
PPP C
ONTROL
R
EGISTER
(A
DDRESS
= 0
X
1703)......340
TRANSMIT ATM CELL PROCESSOR BLOCK.......................................................................................341
T
ABLE
18: T
RANSMIT
ATM C
ELL
P
ROCESSOR
/PPP P
ACKET
P
ROCESSOR
B
LOCK
- R
EGISTER
/A
DDRESS
M
AP
................................ 341
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ONTROL
R
EGISTER
- B
YTE
2 (A
DDRESS
= 0
X
1F01)
344
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ONTROL
R
EGISTER
- B
YTE
1 (A
DDRESS
= 0
X
1F02)
345
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ONTROL
- B
YTE
0 (A
DDRESS
= 0
X
1F03).......347
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
1F07)........349
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM I
NTERRUPT
S
TATUS
R
EGISTER
(A
DDRESS
= 0
X
1F0B)
350
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM I
NTERRUPT
E
NABLE
R
EGISTER
(A
DDRESS
= 0
X
1F0F)
352
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM C
ELL
I
NSERTION
/E
XTRACTION
M
EMORY
C
ONTROL
R
EG
-
ISTER
(0
X
1F13)........................................................................................................................................354
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
C
ELL
I
NSERTION
/E
XTRACTION
M
EMORY
D
ATA
- B
YTE
3 (A
D
-
DRESS
= 0
X
1F14)......................................................................................................................................356
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
C
ELL
I
NSERTION
/E
XTRACTION
M
EMORY
D
ATA
- B
YTE
2 (A
D
-
DRESS
= 0
X
1F15)......................................................................................................................................357
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
C
ELL
I
NSERTION
/E
XTRACTION
M
EMORY
D
ATA
- B
YTE
1 (A
D
-
DRESS
= 0
X
1F16)......................................................................................................................................358
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
C
ELL
I
NSERTION
/E
XTRACTION
M
EMORY
D
ATA
- B
YTE
0 (A
D
-
DRESS
= 0
X
1F17)......................................................................................................................................359
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM I
DLE
C
ELL
H
EADER
B
YTE
1 (A
DDRESS
= 0
X
1F18).
360
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM I
DLE
C
ELL
H
EADER
B
YTE
2 (A
DDRESS
= 0
X
1F19).
360
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM I
DLE
C
ELL
H
EADER
B
YTE
3 (A
DDRESS
= 0
X
1F1A)
361
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM I
DLE
C
ELL
H
EADER
B
YTE
4 (A
DDRESS
= 0
X
1F1B)
361
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
ATM I
DLE
C
ELL
P
AYLOAD
R
EGISTER
(A
DDRESS
= 0
X
1F1F)
362
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
T
EST
C
ELL
H
EADER
B
YTE
- B
YTE
1 (A
DDRESS
= 0
X
1F20)
362
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
T
EST
C
ELL
H
EADER
B
YTE
- B
YTE
2 (A
DDRESS
= 0
X
1F21)
363
T
RANSMIT
ATM C
ELL
P
ROCESSOR
B
LOCK
- T
RANSMIT
T
EST
C
ELL
H
EADER
B
YTE
- B
YTE
3 (A
DDRESS
= 0
X
1F22)