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參數(shù)資料
| 型號： | XRT75VL00DIVTR-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 59/92頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 1CH 52TQFP |
| 標準包裝： | 1,000 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-LQFP |
| 供應商設備封裝： | 52-TQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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XRT75VL00D
57
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.4
The 44.736MHz - 1ppm Case
Throughout each of these cases, we will discuss how the resulting "bit-stuffing" (that was done when mapping
the DS3 signal into SONET) affects the amount of intrinsic jitter and wander that will be present in the DS3
signal, once it is ultimately de-mapped from SONET.
9.2.2.1
The Ideal Case for Mapping DS3 data into an STS-1 Signal (e.g., with no Frequency
Offsets)
Let us assume that we are mapping a DS3 signal, which has a bit rate of exactly 44.736Mbps (with no
frequency offset) into SONET. Further, let us assume that the SONET circuitry within the PTE is clocked at
exactly 51.84MHz (also with no frequency offset), as depicted below.
Given the above-mentioned assumptions, we can state the following.
The DS3 data-stream has a bit-rate of exactly 44.736Mbps
The PTE will create 8000 STS-1 SPE's per second
In order to properly map a DS3 data-stream into an STS-1 data-stream, then each STS-1 SPE must carry
(44.736Mbps/8000 =) 5592 DS3 data bits.
Is there a Problem?
According to Figure 37, each STS-1 SPE only contains 5589 bits that are specifically designated for "DS3 data
bits". In this case, each STS-1 SPE appears to be three bits "short".
No there is a Simple Solution
No, earlier we mentioned that each STS-1 SPE consists of nine (9) "Stuff Opportunity" bits. Therefore, these
three additional bits (for DS3 data) are obtained by using three of these "Stuff Opportunity" bits.
As a
consequence, three (3) of these nine (9) "Stuff Opportunity" bits, within each STS-1 SPE, will carry DS3 data-
bits. The remaining six (6) "Stuff Opportunity" bits will typically function as "stuff" bits.
In summary, for the "Ideal Case"; where there is no frequency offset between the DS3 and the STS-1 bit-rates,
once this DS3 data-stream has been mapped into the STS-1 data-stream, then each and every STS-1 SPE will
have the following "Stuff Opportunity" bit utilization.
3 "Stuff Opportunity" bits will carry DS3 data bits.
6 "Stuff Opportunity" bits will function as "stuff" bits
In this case, this DS3 signal (which has now been mapped into STS-1) will be transported across the SONET
network. As this STS-1 signal arrives at the "Destination PTE", this PTE will extract (or de-map) this DS3 data-
stream from each incoming STS-1 SPE. Now since each and every STS-1 SPE contains exactly 5592 DS3
data bits; then the bit rate of this DS3 signal will be exactly 44.736Mbps (such as it was when it was mapped
into SONET, at the "Source" PTE).
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE
PTE
44.736MHz + 0ppm
DS3_Data_In
STS-1_Data_Out
51.84MHz + 0ppm
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XRT75VL00ES | 功能描述:時鐘合成器/抖動清除器 1CHT3/E3/STS1LIU+A 3.3V VOLTAGE DRIVE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75VL00IV | 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75VL00IV-F | 功能描述:外圍驅(qū)動器與原件 - PCI 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| XRT75VL00IVTR | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
| XRT75VL00IVTR-F | 功能描述:時鐘合成器/抖動清除器 3.3V 1 CH E3/DS3/STS W/JITTER ATTEN RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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