參數(shù)資料
型號(hào)： XRT75R12IB
廠商： Exar Corporation
文件頁(yè)數(shù)： 90/90頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
87
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2007 EXAR Corporation
Datasheet October 2007.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
XRT75R12
REV. 1.0.4
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
REVISION HISTORY
REVISION
DATE
COMMENTS
1.0.0
05/10/05
Final Release Version of XRT75R12 datasheet.
1.0.1
April 2006
1.Added current and power consumption on Table 50, “DC Electrical Characteristics:,” on
page 84.
2. Revised Receive Monitor Enable Bit functional description and Section
3.3.1 description.
3. Updated Table 3, “The ALOS (Analog LOS) Declaration and Clearance Thresholds for a
given setting of REQEN (DS3 and STS-1 Applications),” on page 23.
4. Minor corrections on Transmitter Section of Features Summary on page 2.
5. Minor typo corrections in STS1Clk/12M pin description and in Section
1.0, 3.3, and 4.5,
Table 7 and Table 9.
6. Added Table 2, “Reference Clock Performance Specifications,” on page 19.
1.0.2
12/07/06
1.Corrected package thermal resistance specification.
1.0.3
6/11/07
1. Corrected global register 0x08 and added global registers 0x80 & 0x88.
2. Added (N = [0:11] & M = 0-5 & 8-D) to channelized register titles.
1.0.4
10/26/07
1.Theta-jC thermal value added.
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