參數(shù)資料
型號(hào)： XRT75R12IB
廠商： Exar Corporation
文件頁數(shù)： 23/90頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 12CH 420TBGA
標(biāo)準(zhǔn)包裝： 40
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 12/12
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 420-LBGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 420-TBGA（35x35）
包裝： 托盤
XRT75R12
I
REV. 1.0.4
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
TABLE OF CONTENTS
GENERAL DESCRIPTION.............................................................................................................. 1
APPLICATIONS ............................................................................................................................................................... 1
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75R12 .................................................................................................................................... 1
ORDERING INFORMATION .................................................................................................................... 1
FEATURES..................................................................................................................................................................... 2
TRANSMIT INTERFACE CHARACTERISTICS ....................................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ......................................................................................................................... 2
TABLE OF CONTENTS ............................................................................................................ I
PIN DESCRIPTIONS (BY FUNCTION) ........................................................................................... 3
SYSTEM-SIDE TRANSMIT INPUT AND TRANSMIT CONTROL PINS....................................................................................... 3
SYSTEM-SIDE RECEIVE OUTPUT AND RECEIVE CONTROL PINS ....................................................................................... 6
RECEIVE LINE SIDE PINS ............................................................................................................................................... 8
CLOCK INTERFACE......................................................................................................................................................... 9
GENERAL CONTROL PINS ............................................................................................................................................ 10
POWER SUPPLY PINS .................................................................................................................................................. 12
GROUND PINS ............................................................................................................................................................. 13
TABLE 1: PIN LIST BY PIN NUMBER ....................................................................................................................................................... 14
FUNCTIONAL DESCRIPTION ...................................................................................................... 18
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ....................................... 18
1.1 NETWORK ARCHITECTURE ......................................................................................................................... 18
FIGURE 2. NETWORK REDUNDANCY ARCHITECTURE .............................................................................................................................. 18
2.0 CLOCK SYNTHESIZER ....................................................................................................................... 19
FIGURE 3. SIMPLIFIED BLOCK DIAGRAM OF THE INPUT CLOCK CIRCUITRY DRIVING THE MICROPROCESSOR ............................................ 19
TABLE 2: REFERENCE CLOCK PERFORMANCE SPECIFICATIONS.............................................................................................................. 19
2.1 CLOCK DISTRIBUTION ................................................................................................................................. 20
FIGURE 4. CLOCK DISTRIBUTION CONGIFURED IN E3 MODE WITHOUT USING SFM ................................................................................ 20
3.0 THE RECEIVER SECTION .................................................................................................................. 21
FIGURE 5. RECEIVE PATH BLOCK DIAGRAM .......................................................................................................................................... 21
3.1 RECEIVE LINE INTERFACE .......................................................................................................................... 21
FIGURE 6. RECEIVE LINE INTERFACECONNECTION................................................................................................................................. 21
3.2 ADAPTIVE GAIN CONTROL (AGC) .............................................................................................................. 21
3.3 RECEIVE EQUALIZER ................................................................................................................................... 21
FIGURE 7. ACG/EQUALIZER BLOCK DIAGRAM ....................................................................................................................................... 22
3.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS .............................................................................................. 22
3.4 CLOCK AND DATA RECOVERY ................................................................................................................... 22
3.4.1 DATA/CLOCK RECOVERY MODE ............................................................................................................................ 22
3.4.2 TRAINING MODE........................................................................................................................................................ 22
3.5 LOS (LOSS OF SIGNAL) DETECTOR ........................................................................................................... 22
3.5.1 DS3/STS-1 LOS CONDITION ..................................................................................................................................... 22
TABLE 3: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF REQEN (DS3 AND STS-1 AP-
PLICATIONS
).......................................................................................................................................................................... 23
3.5.2 DISABLING ALOS/DLOS DETECTION ..................................................................................................................... 23
3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23
FIGURE 8. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775 .................................................................................................. 23
FIGURE 9. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775................................................................................................... 24
3.5.4 INTERFERENCE TOLERANCE.................................................................................................................................. 24
FIGURE 10. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1 ...................................................................................................... 24
FIGURE 11. INTERFERENCE MARGIN TEST SET UP FOR E3. ................................................................................................................... 24
TABLE 4: INTERFERENCE MARGIN TEST RESULTS ................................................................................................................................. 25
3.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 25
FIGURE 12. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING ........................................................................................................ 25
3.6 B3ZS/HDB3 DECODER .................................................................................................................................. 26
4.0 THE TRANSMITTER SECTION ........................................................................................................... 27
FIGURE 13. TRANSMIT PATH BLOCK DIAGRAM ...................................................................................................................................... 27
4.1 TRANSMIT DIGITAL INPUT INTERFACE ..................................................................................................... 27
FIGURE 14. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75R12 (DUAL-RAIL DATA) .............................................. 27
FIGURE 15. TRANSMITTER TERMINAL INPUT TIMING............................................................................................................................... 28
FIGURE 16. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED) .................................................................. 28
4.2 TRANSMIT CLOCK ........................................................................................................................................ 29
相關(guān)PDF資料
PDF描述
ISL267450AIUZ-T IC INTERFACE
MS3116P16-8P CONN PLUG 8POS STRAIGHT W/PINS
IDT72V815L15PFI IC FIFO SYNC 512X18 15NS 128QFP
MS27513E8F35SD CONN RCPT 6POS BOX MNT W/SCKT
MS3101E16-12S CONN RCPT 1POS FREE HNG W/SCKT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT75R12IB-F 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
XRT75R12IB-L 功能描述:LIN 收發(fā)器 Attenuator RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT75VL00 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00_08 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00D 制造商:EXAR 制造商全稱:EXAR 功能描述:E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*