參數(shù)資料
型號(hào)： XRT75R12IB
廠商： EXAR CORP
元件分類： 數(shù)字傳輸電路
英文描述： TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
中文描述： DATACOM, PCM TRANSCEIVER, PBGA420
封裝： 35 X 35 MM, TBGA-420
文件頁數(shù)： 40/89頁
文件大小： 457K
代理商： XRT75R12IB
XRT75R12
REV. P1.0.2
PRELIMINARY
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
37
5.0
There are three fundamental parameters that describe circuit performance relative to jitter
Jitter Tolerance
Jitter Transfer
Jitter Generation
5.1
J
ITTER
T
OLERANCE
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 25, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence. Input jitter tolerance requirements are specified in terms of
compliance with jitter mask which is represented as a combination of points. Each point corresponds to a
minimum amplitude of sinusoidal jitter at a given jitter frequency.
JITTER
5.1.1
Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II.
The jitter tolerance requirement for Category II is the most stringent. Figure 26 shows the jitter tolerance curve
as per GR-499 specification.
DS3/STS-1 Jitter Tolerance Requirements
F
IGURE
25. J
ITTER
T
OLERANCE
M
EASUREMENTS
FREQ
Synthesizer
Pattern
Generator
DUT
XRT75R12
Error
Detector
Modulation
Freq.
Data
Clock
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