參數(shù)資料
型號: XRT75R12D
廠商: Exar Corporation
英文描述: TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: 第十二章通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁數(shù): 125/131頁
文件大?。?/td> 717K
代理商: XRT75R12D
PRELIMINARY
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. P1.0.1
120
HOW MAJOR PATTERN B IS SYNTHESIZED
MAJOR PATTERN B is created (by the Mapper IC) by:
Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times.
Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
pon completion of the 35th transmission of MINOR PATTERN P2, MINOR PATTERN P3 is transmitted once.
Figure 69 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN B.
Hence, MAJOR PATTERN B consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses.
These 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 STS-1 (or 51.84MHz)
clock periods.
PUTTING THE PATTERNS TOGETHER
Finally, the DS3 to OC-N Mapper IC clock output is reproduced by doing the following.
MAJOR PATTERN A is transmitted two times (repeatedly).
After the second transmission of MAJOR PATTERN A, MAJOR PATTERN B is transmitted once.
Then the whole process repeats.
Throughout the remainder of this document, we will refer to this particular pattern as the "SUPER PATTERN".
Figure 70 presents an illustration of this "SUPER PATTERN" which is output via the Mapper IC.
F
IGURE
68. I
LLUSTRATION
OF
MINOR PATTERN P3
F
IGURE
69. I
LLUSTRATION
OF
P
ROCEDURE
WHICH
IS
USED
TO
S
YNTHESIZE
PATTERN B
1 2 3 4 5
6
PATTERN P1
PATTERN P2
Repeats 63 Times
Repeats 35 Times
PATTERN P3
Transmitted 1 Time
相關PDF資料
PDF描述
XRT75R12DIB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75R12 TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75R12IB TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00 E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
XRT75VL00IV E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
相關代理商/技術參數(shù)
參數(shù)描述
XRT75R12D_06 制造商:EXAR 制造商全稱:EXAR 功能描述:TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET
XRT75R12D_07 制造商:EXAR 制造商全稱:EXAR 功能描述:TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET
XRT75R12DES 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
XRT75R12DIB 功能描述:網(wǎng)絡控制器與處理器 IC 12CH E3/DS3/STS W/JITTER R3 TECH RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT75R12DIB-F 功能描述:網(wǎng)絡控制器與處理器 IC 12 Channel 3.3V-5V temp -45 to 85C RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray