參數(shù)資料
型號： XRT75R06IB-F
廠商： Exar Corporation
文件頁數(shù)： 32/63頁
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 6CH 217BGA
標準包裝： 126
類型： 線路接口裝置（LIU）
驅動器/接收器數(shù)： 6/6
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類型： 表面貼裝
封裝/外殼： 217-BBGA
供應商設備封裝： 217-BGA（23x23）
包裝： 托盤
XRT75R06
á
REV. 1.0.0
SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR
35
5.0
JITTER
There are three fundamental parameters that describe circuit performance relative to jitter
Jitter Tolerance
Jitter Transfer
Jitter Generation
5.1
JITTER TOLERANCE
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 26, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence.
Input jitter tolerance requirements are specified in terms of
compliance with jitter mask which is represented as a combination of points. Each point corresponds to a
minimum amplitude of sinusoidal jitter at a given jitter frequency.
5.1.1
DS3/STS-1 Jitter Tolerance Requirements
Bellcore GR-499 CORE specifies the minimum requirement of jitter tolerance for Category I and Category II.
The jitter tolerance requirement for Category II is the most stringent. Figure 27 shows the jitter tolerance curve
as per GR-499 specification.
FIGURE 26. JITTER TOLERANCE MEASUREMENTS
FREQ
Synthesizer
Pattern
Generator
DUT
XRT75R06
Error
Detector
Modulation
Freq.
Data
Clock
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