參數(shù)資料
型號(hào): XRT75L04D
廠商: Exar Corporation
英文描述: FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: 四通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁(yè)數(shù): 48/98頁(yè)
文件大?。?/td> 536K
代理商: XRT75L04D
XRT75L04D
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
á
REV. 1.0.1
44
0x03 (ch 0)
0x0B (ch 1)
0x13 (ch 2)
0x1B (ch 3)
Read
Only
Alarm Sta-
tus
D0
DMO_n
This bit is set when no transitions on the TTIP/
TRING have been detected for 128 ± 32 TxCLK
periods.
0
D1
RLOS_n
This bit is set every time the receiver declares an
LOS condition.
0
D2
RLOL_n
This bit is set every time when the receiver declares
a Loss of Lock condition.
0
D3
FL_n
This bit is set every time the FIFO in the Jitter Atten-
uator is within 2 bit of underflow/overflow condition.
0
D4
ALOS_n
This bit is set every time the receiver declares Ana-
log LOS condition.
0
D5
DLOS_n
This bit is set every time the receiver declares Digital
LOS condition.
0
D6
PRBSLS_n This bit is set every time the PRBS detector is not in
sync.
0
D7
Reserved
0x04 (ch 0)
0x0C (ch 1)
0x14 (ch 2)
0x!C (ch 3)
R/W
Transmit
Control
D0
TxLEV_n
Set this bit for cable length greater than 225
feet.
N
OTE
:
See section 4.03 for detailed description.
0
D1
TxClkINV_
n
Set this bit to sample the data on TPOS/TNEG pins
on the rising edge of TxClk.
0
D2
TAOS_n
Set this bit to send a continuous stream of marks
(All Ones) out at the TTIP and TRing pins.
0
D3
Reserved
D4
INSPRBS_
n
Setting this bit causes the PRBS generator to insert
a single-bit error onto the transmit PRBS data
stream .
N
OTE
:
PRBS Generator/Detector must be enabled
for this bit to have any effect.
0
D5
TxMON_n
Setting this bit causes the driver monitor its own
transmit driver. When the transmit failure is
detected, DMO output pin goes “High” and DMOIS
bit is set.
When this bit is “0”, MTIP and MRing are connected
to other transmit channel for monitoring.
0
D7-D6
Reserved
T
ABLE
21: R
EGISTER
M
AP
D
ESCRIPTION
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
BIT#
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
相關(guān)PDF資料
PDF描述
XRT75L04DIV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L04IV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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