參數(shù)資料
型號(hào): XRT75L04D
廠商: Exar Corporation
英文描述: FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
中文描述: 四通道E3/DS3/STS-1線路接口單元與SONET DESYNCHRONIZER
文件頁數(shù): 47/98頁
文件大?。?/td> 536K
代理商: XRT75L04D
á
REV. 1.0.1
XRT75L04D
FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
43
T
ABLE
21: R
EGISTER
M
AP
D
ESCRIPTION
A
DDRESS
(H
EX
)
T
YPE
R
EGISTER
N
AME
BIT#
S
YMBOL
D
ESCRIPTION
D
EFAULT
V
ALUE
0x01 (ch 0)
0x09 (ch 1)
0x11 (ch 2)
0x19 (ch 3)
R/W
Interrupt
Enable
(source
level)
D0
DMOIE_n
Set this bit to enable an interrupt when the no trans-
mission detected on channel output.
0
D1
RLOSIE_n Writng a “1” to this bit enables an interrupt when
Recieve Los of Signal is detected.
0
D2
RLOLIE_n
Writing a “1” to this bit enables an interrupt when
Receive Loss of Lock condition is detected
0
D3
FLIE_n
Writing a “1” to this bit enables the interrupt when
the FIFO Limit of the Jitter Attenuator is within 2 bits
of overflow/underflow condition.
N
OTE
:
This bit field is ignored when the Jitter
Attenuator is disabled.
0
D4
PRBSERIE
_n
Set this bit to enable the interrupt when the PRBS
error is detected.
0
D5
PRBSERC
NTIE_n
Set this bit to enable the interrupt when the PRBS
error count register saturates.
0
D7-D6
Reserved
0x02 (ch 0)
0x0A (ch 1)
0x12 (ch 2)
0x1A (ch 3)
Reset
on
Read
Interrupt
Status
(source
level)
D0
DMOIS_n
This bit is set every time a DMO status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D1
RLOSIS_n This bit is set every time a RLOS status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D2
RLOLIS_n
This bit is set every time a RLOL status change has
occurred since the last cleared interrupt. This bit is
cleared when the register bit is read.
0
D3
FLIS_n
This bit is set every time a FIFO Limit status change
has occurred since the last cleared interrupt. This bit
is cleared when the register bit is read.
0
D4
PRBSERIS
_n
This bit is set when the PRBS error occurs.
0
D5
PRBSERC
NTIS_n
This bit is set when the PRBS error count register
saturates.
0
D7-D6
Reserved
相關(guān)PDF資料
PDF描述
XRT75L04DIV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L04 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L04IV FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER
XRT75L06D SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L06DIB SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
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XRT75L04DES 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 4CH T3/E3/STS1 LIU+DESYNCH 3.3V RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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