
á
THREE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
XRT75L03D
REV. 1.0.0
II
5.1 AGC/E
QUALIZER
: ............................................................................................................................................ 44
Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 44
5.1.1 Interference Tolerance: ..................................................................................................................... 45
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 45
5.2 C
LOCK
AND
D
ATA
R
ECOVERY
: ......................................................................................................................... 46
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 46
T
ABLE
9: I
NTERFERENCE
M
ARGIN
T
EST
R
ESULTS
.............................................................................................. 46
5.3 B3ZS/HDB3 D
ECODER
: .................................................................................................................................. 47
5.4 LOS (L
OSS
OF
S
IGNAL
) D
ETECTOR
: ................................................................................................................ 47
5.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 47
D
ISABLING
ALOS/DLOS D
ETECTION
: ......................................................................................................... 47
5.4.2 E3 LOS Condition: ............................................................................................................................. 47
T
ABLE
10: T
HE
ALOS (A
NALOG
LOS) D
ECLARATION
AND
C
LEARANCE
T
HRESHOLDS
FOR
A
GIVEN
SETTING
OF
LOSTHR
AND
REQEN (DS3
AND
STS-1 A
PPLICATIONS
) ................................................................... 47
Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 48
Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 48
5.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 49
6.0 Jitter: ................................................................................................................................................. 49
6.1 J
ITTER
T
OLERANCE
- R
ECEIVER
: ...................................................................................................................... 49
6.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 49
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 49
6.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 50
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 50
Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 50
6.2 J
ITTER
T
RANSFER
- R
ECEIVER
/T
RANSMITTER
: .................................................................................................. 51
6.3 J
ITTER
A
TTENUATOR
: ...................................................................................................................................... 51
T
ABLE
11: J
ITTER
A
MPLITUDE
VERSUS
M
ODULATION
F
REQUENCY
(J
ITTER
T
OLERANCE
) ..................................... 51
T
ABLE
12: J
ITTER
T
RANSFER
S
PECIFICATION
/R
EFERENCES
............................................................................... 51
6.3.1 Jitter Generation: ............................................................................................................................... 52
7.0 Serial Host interface: ....................................................................................................................... 52
T
ABLE
13: J
ITTER
T
RANSFER
P
ASS
M
ASKS
....................................................................................................... 52
Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 52
T
ABLE
14: F
UNCTIONS
OF
SHARED
PINS
............................................................................................................ 53
T
ABLE
15: XRT75L03D R
EGISTER
M
AP
- Q
UICK
L
OOK
..................................................................................... 54
................................................................................................................................................................. 56
THE REGISTER MAP AND DESCRIPTION FOR THE XRT75L03D 3-CHANNEL DS3/E3/STS-1 LIU IC ..
56
Legend: ..................................................................................................................................................................56
T
ABLE
16: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75L03D 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC ................................................................................................................................. 56
THE GLOBAL/CHIP-LEVEL REGISTERS ............................................................................................... 58
................................................................................................................................................................. 58
REGISTER DESCRIPTION - GLOBAL REGISTERS .............................................................................. 58
T
ABLE
17: L
IST
AND
A
DDRESS
L
OCATIONS
OF
G
LOBAL
R
EGISTERS
.................................................................... 58
T
ABLE
18: APS/R
EDUNDANCY
C
ONTROL
R
EGISTER
- CR0 (A
DDRESS
L
OCATION
= 0
X
00) .................................. 58
T
ABLE
19: B
LOCK
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- CR32 (A
DDRESS
L
OCATION
= 0
X
20) ......................... 61
T
ABLE
20: B
LOCK
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- CR33 (A
DDRESS
L
OCATION
= 0
X
21) ......................... 62
T
ABLE
21: D
EVICE
/P
ART
N
UMBER
R
EGISTER
- CR62 (A
DDRESS
L
OCATION
= 0
X
3E) .......................................... 63
................................................................................................................................................................. 64
THE PER-CHANNEL REGISTERS ......................................................................................................... 64
T
ABLE
22: C
HIP
R
EVISION
N
UMBER
R
EGISTER
- CR63 (A
DDRESS
L
OCATION
= 0
X
3F) ........................................ 64
T
ABLE
23: C
OMMAND
R
EGISTER
A
DDRESS
M
AP
,
WITHIN
THE
XRT75L03D 3-C
HANNEL
DS3/E3/STS-1 LIU
W
/ J
ITTER
A
TTENUATOR
IC ................................................................................................................................. 64
REGISTER DESCRIPTION - PER CHANNEL REGISTERS ................................................................... 66
T
ABLE
24: S
OURCE
L
EVEL
I
NTERRUPT
E
NABLE
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
01 ................. 66
T
ABLE
25: S
OURCE
L
EVEL
I
NTERRUPT
S
TATUS
R
EGISTER
- C
HANNEL
0 A
DDRESS
L
OCATION
= 0
X
02 ................. 68