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參數(shù)資料
型號(hào)： XRT73L02MIVTR-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 37/46頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 2CH 100TQFP
標(biāo)準(zhǔn)包裝： 1,000
類(lèi)型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 2/2
規(guī)程： DS3，E3，STS-1
電源電壓： 3.135 V ~ 3.465 V
安裝類(lèi)型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
XRT73L02M
xr
TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.0.0
40
8.0
DIAGNOSTIC FEATURES:
8.1
PRBS GENERATOR AND DETECTOR:
The XRT73L02M contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. This feature is only available in Host mode. With the PRBSEN_n bit = “1”, the transmitter
will send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detec-
tor is also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go
“Low” to indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRB-
SLS bit will be set to “1” and RNEG/LCV pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for one RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to IN-
SPRBS bit and followed by a “1”.
Figure 25 shows the status of RNEG/LCV pin when the XRT73L02M is configured in PRBS mode.
NOTE: In PRBS mode, the device is forced to operate in Single-Rail Mode.
8.2
LOOPBACKS:
The XRT73L02M offers three loop back modes for diagnostic purposes. In Hardware mode, the loop back
modes are selected via the RLB_n and LLB_n pins. In Host mode, the RLB_n and LLB_n bits n the Channel
control registers select the loop back modes.
8.2.1
ANALOG LOOPBACK:
In this mode, the transmitter outputs (TTIP_n and TRING_n) are connected internally to the receiver inputs
(RTIP_n and RRING_n) as shown in Figure 26. Data and clock are output at RCLK_n, RPOS_n and RNEG_n
pins for the corresponding transceiver. Analog loop back exercises most of the functional blocks of the device
including the jitter attenuator which can be selected in either the transmit or receive path.
XRT73L02M can be configured in Analog Loopback either in Hardware mode via the LLB_n and RLB_n pins or
in Host mode via LLB_n and RLB_n bits in the channel control registers.
NOTES:
1. In the Analog loopback mode, data is also output via TTIP_n and TRING_n pins.
2. Signals on the RTIP_n and RRING_n pins are ignored during analog loop back.
FIGURE 24. PRBS MODE
RClk
RNEG/LCV
SYNC LOSS
PRBS SYNC
Single Bit Error
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