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XRT73L02
2 CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
PRELIMINARY
REV. P1.1.0
45
4.0
DIAGNOSTIC FEATURES OF THE XRT73L02
The XRT73L02 supports equipment diagnostic activi-
ties by supporting the following Loop-Back modes in
each channel in the XRT73L02:
Analog Local Loop-Back
Digital Local Loop-Back
Remote Loop-Back
4.1
T
HE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
When a given channel in the XRT73L02 is configured
to operate in the Analog Local Loop-Back Mode, it ig-
nores any signals that are input to its RTIP_(n) and
RRing_(n) input pins. The Transmitting Terminal
Equipment transmits clock and data into this channel
via the TPData_(n), TNData_(n) and TxClk_(n) input
pins. This data is processed through the Transmit
Clock Duty Cycle Adjust PLL and the HDB3/B3ZS
Encoder. Finally, this data outputs to the line via the
TTIP_(n) and TRing_(n) output pins. Additionally, this
data loops back into the Attenuator/Receive Equalizer
Block. This data is processed through the entire Re-
ceive Section of the channel. After this post-Loop-
Back data has been processed through the Receive
Section, it outputs to the Near-End Receiving Termi-
nal Equipment via the RPOS_(n), RNEG_(n) and
RxClk_(n) output pins.
Figure 27 illustrates the path the data takes in a given
channel of the XRT73L02 when it is configured to op-
erate in the Analog Local Loop-Back Mode.
A given channel in the XRT73L02 can be configured
to operate in the Analog Local Loop-Back Mode by
employing either one of the following two steps:
N
OTE
:
See Table 2 for a description of Command Registers
and Addresses for the different channels.
a. Operating in the HOST Mode
To configure Channel (n) to operate in the Analog Lo-
cal Loop-Back Mode, write a "1" into the LLB_(n) bit-
field and a "0" into the RLB_(n) bit-field in Command
Register CR4.
COMMAND REGISTER CR4-(n)
b. Operating in the Hardware Mode
F
IGURE
27. A
CHANNEL
IN
THE
XRT73L02
OPERATING
IN
THE
A
NALOG
L
OCAL
L
OOP
-B
ACK
M
ODE
EAGC/
Peak
Detector
LOS Detecto
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR_(n)
SDI
SDO
SClk
CS
REGR
RTIP_(n)
RRing_(n)
REQEN_(n)
RxClk_(n)
RPOS_(n)
RNEG_(n)
LCV_(n)
ENDECDIS
RLOS_(n)
LLB_(n)
RLB_(n)
TAOS_(n)
TPData_(n)
TNData_(n)
TxClk_(n)
Notes:
1. (n) = 0 or 1 for respective Channels
2. Serial Processor Interface input pins are shared by the two Channels in HOST Mode and redefined in Hardware Mode.
RLOL_(n) EXClk_(n)
Device
Monitor
MTIP_(n)
MRing_(n)
Transmit
Logic
Duty Cycle Adjust
TxLEV_(n)
TxOFF_(n)
DMO_(n)
TTIP_(n)
TRing_(n)
Pulse
Shaping
HDB3/
B3ZS
Encoder
Serial
Processor
Interface
Analog Local
Loop-Back Path
D4
D3
D2
D1
D0
X
STS-1/DS3_ Ch_(n) E3_ Ch_(n) LLB_(n) RLB_(n)
X
X
X
1
0