參數(shù)資料
型號(hào)： XRT7300IV
廠商： Exar Corporation
文件頁(yè)數(shù)： 1/55頁(yè)
文件大?。?/td> 0K
描述： IC LIU E3/DS3/STS-1 SGL 44TQFP
標(biāo)準(zhǔn)包裝： 160
類型： 線路接口裝置（LIU）
驅(qū)動(dòng)器/接收器數(shù)： 1/1
規(guī)程： DS3，E3，STS-1
電源電壓： 4.75 V ~ 5.25 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
Exar Corporation 48720 Kato Road, Fremont CA, 94538 (510) 668-7000 FAX (510) 668-7017 www.exar.com
XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
MAY 2011
REV. 1.1.2
GENERAL DESCRIPTION
The XRT7300 DS3/E3/STS-1 Line Interface Unit is
designed to be used in DS3, E3 or SONET STS-1 ap-
plications and consists of a line transmitter and re-
ceiver integrated on a single chip.
XRT7300 can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates.
In the transmit direction, the XRT7300 encodes input
data to either B3ZS (for DS3/STS-1 applications) or
HDB3 (for E3 applications) format and converts the
data into the appropriate pulse shapes for transmis-
sion over coaxial cable via a 1:1 transformer.
In the receive direction the XRT7300 performs equal-
ization on incoming signals, performs Clock Recov-
ery, decodes data from either B3ZS or HDB3 format,
converts the receive data into TTL/CMOS format,
checks for LOS or LOL conditions and detects and
declares the occurrence of line code violations.
The XRT7300 also contains a 4-Wire Microprocessor
Serial Interface for accessing the on-chip Command
registers.
FEATURES
Meets E3/DS3/STS-1 Jitter Tolerance Require-
ments
Full Loop-Back Capability
Transmit and Receive Power Down Modes
Full Redundancy Support
Contains a 4-Wire Microprocessor Serial Interface
Uses Minimum External components
Requires Single +5V Power Supply
-40°C to +85°C Operating Temperature Range
Available in a 44 pin TQFP package
APPLICATIONS
Interfaces to E3, DS3 or SONET STS-1 Networks
CSU/DSU Equipment
PCM Test Equipment
Fiber Optic Terminals
Multiplexers
NOTE: This Device is Protected by US Patent # 6,157,270
FIGURE 1. BLOCK DIAGRAM OF THE XRT7300
AGC/
Equalizer
Serial
Processor
Interface
Peak
Detector
LOS Detector
Slicer
Clock
Recovery
Data
Recovery
Invert
Loop MUX
HDB3/
B3ZS
Decoder
LOSTHR
SDI
SDO/(LCV)
SClk
CS
REGRESET
RTIP
RRING
REQDIS
Device
Monitor
MTIP
MRING
DMO
Transmit
Logic
Duty Cycle Adjust
TTIP
TRING
Pulse
Shaping
HDB3/
B3ZS
Encoder
E3
STS-1/DS3
Host/(HW)
RLOL EXCLK
ICT
RCLK2INV
Tx
Control
DECODIS
RLOS
LLB
RLB
ENCODIS
TAOS
TPDATA
TNDATA
TClk
TXLEV
TXOFF
RCLK1
RNEG
RPOS
LCV/(RCLK2)
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