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參數(shù)資料
| 型號： | XRT7300IV-F |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 31/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU E3/DS3/STS-1 SGL 44TQFP |
| 標準包裝： | 160 |
| 類型： | 線路接口裝置（LIU） |
| 驅(qū)動器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤 |
| 其它名稱： | 1016-1635 XRT7300IV-F-ND |
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XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.2
33
be disabled by writing a “1” into the ALOSDIS bit-field
in Command Register 2 as depicted below.
NOTE: Setting both the ALOSDIS and DLOSDIS bit-fields
to “1” disables LOS Declaration in the XRT7300.
2. The Digital LOS (DLOS) Declaration/Clear-
ance Criteria
The XRT7300 declare a Digital LOS (DLOS) condi-
tion if the XRT7300 detects 160±32 or more consecu-
tive “0’s” in the incoming data.
The XRT7300 clears DLOS if it detects four consecu-
tive sets of 32 bit-periods each of which contains at
least 10 “1’s” (e.g., average pulse density of greater
than 33%).
Monitoring the State of DLOS
If the XRT7300 is operating in the HOST Mode, the
state of DLOS can be polled or monitored by reading
in the contents of Command Register 0 as shown.
If the DLOS bit-field contains a “1”, the XRT7300 is
currently declaring a DLOS condition. If the DLOS
bit-field contains a “0”, the device is NOT currently
declaring the DLOS condition.
Disabling the DLOS Detector
It is useful to disable the DLOS Detector in the
XRT7300 for debugging purposes. If the XRT7300 is
operating in the HOST Mode, the DLOS Detector can
be disabled by writing a “1” into the DLOSDIS bit-field
in Command Register 2.
NOTE: Setting both the ALOSDIS and DLOSDIS bit-fields
to a “1” disables LOS Declaration in the XRT7300.
3.6.3
Muting the Recovered Data while the LOS
is being Declared
In some applications it is not desirable for the
XRT7300 E3/DS3/STS-1 LIU to recover data and
route it to the Receiving Terminal while the LIU is de-
claring an LOS condition. Consequently, the
XRT7300 includes a LOS Muting feature. This fea-
ture, if enabled, causes the XRT7300 to halt trans-
mission of the recovered data to the Receiving Termi-
nal while the LOS condition is True. In this case, the
RPOS and RNEG output pins are forced to “0”. Once
the LOS condition has been cleared, the XRT7300
resumes the transmission of the recovered data to
the Receiving Terminal. The XRT7300 allows en-
abling of the Muting Upon LOS feature by either of
the following means.
If the XRT7300 is Operating in the Hardware
Mode:
The Muting Upon LOS feature is enabled by pulling
the LOSMUTEN input pin (pin 19) to VDD.
If the XRT7300 is Operating in the HOST Mode:
To enable this feature, access the Microprocessor
Serial Interface and write a “1” into the LOSMUT bit-
field in Command Register 3.
NOTE: The XRT7300 automatically declares an LOS Con-
dition any time it has been configured to operate in either
the Analog Local Loop-Back or Digital Local Loop-Back
Modes. Consequently, MUTing -upon -LOS must be dis-
abled prior to configuring the device to operate in either of
these local Loop-Back modes.
3.7
ROUTING THE RECOVERED TIMING AND DATA
INFORMATION TO THE RECEIVING TERMINAL
EQUIPMENT
The XRT7300 ultimately takes the Recovered Timing
and Data information, converts it into CMOS levels
and routes it to the Receiving Terminal Equipment via
the RPOS, RNEG, RCLK1 and RCLK2 output pins.
The XRT7300 can deliver the recovered data and
clock information to the Receiving Terminal in either a
Single-Rail or Dual-Rail format.
Routing Dual-Rail Format Data to the Receiving
Terminal Equipment
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
DECODIS ENCODIS ALOSDIS DLOSDIS
REQDIS
X
1
X
COMMAND REGISTER CR0 (ADDRESS = 0X00)
D4
D3
D2
D1
D0
RLOL
RLOS
ALOS
DLOS
DMO
Read
Only
Read
Only
Read
Only
Read
Only
Read
Only
COMMAND REGISTER CR2 (ADDRESS = 0X02)
D4
D3
D2
D1
D0
DECODIS ENCODIS ALOSDIS DLOSDIS
REQDIS
X
1
X
COMMAND REGISTER CR3 (ADDRESS = 0X03)
D4
D3
D2
D1
D0
RNRZ
LOSMUT
CLK2DIS RCLK2INV CLK1INV
X
1
X
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