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參數(shù)資料
| 型號(hào)： | XRT7300IV-F |
| 廠(chǎng)商： | Exar Corporation |
| 文件頁(yè)數(shù)： | 16/55頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU E3/DS3/STS-1 SGL 44TQFP |
| 標(biāo)準(zhǔn)包裝： | 160 |
| 類(lèi)型： | 線(xiàn)路接口裝置（LIU） |
| 驅(qū)動(dòng)器/接收器數(shù)： | 1/1 |
| 規(guī)程： | DS3，E3，STS-1 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 44-LQFP |
| 供應(yīng)商設(shè)備封裝： | 44-TQFP（10x10） |
| 包裝： | 托盤(pán) |
| 其它名稱(chēng)： | 1016-1635 XRT7300IV-F-ND |
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XRT7300
E3/DS3/STS-1 LINE INTERFACE UNIT
REV. 1.1.2
19
The HOST Mode
To configure the XRT7300 to operate in the HOST
Mode, connect the HOST/HW input pin (pin 18) to
VDD.
When the XRT7300 is operating in the HOST Mode,
the following is true:
1. The Microprocessor Serial Interface block is
enabled. Many configuration selections are
made by writing the appropriate data into the on-
chip Command Registers via the Microprocessor
Serial Interface.
2. All of the following input pins are disabled:
Pin 1 - TXLEV
Pin 2 - TAOS
Pin 12 - REQDIS
Pin 14 - LLB
Pin 15 - RLB
Pin 16 - STS-1/DS3
Pin 17 - E3
Pin 35 - TXOFF
Tie each of these pins to GND if the XRT7300 IC is to
be operated in the HOST Mode.
Please see Section 5.0 for a detailed description on
operating the Microprocessor Serial Interface or the
on-chip Command Registers.
1.0
SELECTING THE DATA RATE
The XRT7300 can be configured to support the E3
(34.368 Mbps), DS3 (44.736 Mbps) or the SONET
STS-1 (51.84 Mbps) rates. Selection of the data rate
is dependent on whether the XRT7300 is operating in
the Hardware or HOST Mode.
A. When operating in the Hardware Mode.
To configure the XRT7300 for the desired data rate,
the E3 and the STS-1/DS3 pins must be set to the
appropriate logic states shown in Table 2.
B. When operating in the HOST Mode.
To configure the XRT7300 for the desired data rate,
appropriate values need to be written into the STS-1/
DS3 and E3 bit-fields in Command Register CR4.
Table 3 relates the values of these two bit-fields with
respect to the selected data rates.
The results of making these selections are:
1. The VCO Center Frequency of the Clock Recov-
ery Phase-Locked-Loop is configured to match
the selected data rate.
2. The B3ZS/HDB3 Encoder and Decoder blocks
are configured to support B3ZS Encoding/Decod-
ing if the DS3 or STS-1 data rates were selected
or,
3. The B3ZS/HDB3 Encoder and Decoder blocks
are configured to support HDB3 Encoding/
Decoding if the E3 data rate was selected.
4. The on-chip Pulse-Shaping circuitry is configured
to generate Transmit Output pulses of the correct
TABLE 2: SELECTING THE DATA RATE FOR THE XRT7300 VIA THE E3 AND STS-1/DS3 INPUT PINS (HARDWARE
MODE)
DATA RATE
STATE OF E3 PIN
(PIN 17)
STATE OF STS-1/DS3 PIN
(PIN 16)
MODE OF B3ZS/HDB3 ENCODER/
DECODER BLOCKS
E3 (34.368 Mbps)
VDD
X (Don’t Care)
HDB3
DS3 (44.736 Mbps)
0
B3ZS
STS-1 (51.84 Mbps)
0
VDD
B3ZS
COMMAND REGISTER CR4 (ADDRESS = 0X04)
D4
D3
D2
D1
D0
X
STS-1/DS3
E3
LLB
RLB
X
TABLE 3: SELECTING THE DATA RATE FOR THE
XRT7300 VIA THE STS-1/DS3 AND THE E3 BIT-FIELDS
WITHIN COMMAND REGISTER CR4 (HOST MODE)
SELECTED DATA RATE
STS-1/DS3
E3
E3
Don't Care
1
DS3
0
STS-1
1
0
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